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authorNeel Gala <neelgala@incoresemi.com>2022-04-08 17:53:54 +0530
committerNeel Gala <neelgala@incoresemi.com>2022-04-08 20:11:59 +0530
commit5c2670bd8fb784f479cfb56173e3cf77eec28bf4 (patch)
treec02dcf2b8fa8e9af65a4963900afdb61ec28e86d
parentf2fd4900318db42d2c7ab9495645a161ef8de4fd (diff)
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migrate Zbb-Extension opcodes
- aliases have been revised to use $pseudo_op syntax - split the instructions into multiple files as per new file naming policy - some pseudo ops depend on unratified instructions.
-rw-r--r--opcodes-rv64zbb13
-rw-r--r--rv32_zbb3
-rw-r--r--rv64_zbb9
-rw-r--r--rv_zbb (renamed from opcodes-rv32zbb)23
4 files changed, 19 insertions, 29 deletions
diff --git a/opcodes-rv64zbb b/opcodes-rv64zbb
deleted file mode 100644
index c2ab552..0000000
--- a/opcodes-rv64zbb
+++ /dev/null
@@ -1,13 +0,0 @@
-# RV64Zbb additions to RV32Zbb
-
-rolw rd rs1 rs2 31..25=48 14..12=1 6..2=0x0E 1..0=3
-rorw rd rs1 rs2 31..25=48 14..12=5 6..2=0x0E 1..0=3
-
-roriw rd rs1 31..26=24 25=0 shamtw 14..12=5 6..2=0x06 1..0=3
-
-clzw rd rs1 31..20=0x600 14..12=1 6..2=0x06 1..0=3
-ctzw rd rs1 31..20=0x601 14..12=1 6..2=0x06 1..0=3
-cpopw rd rs1 31..20=0x602 14..12=1 6..2=0x06 1..0=3
-
-rev8 rd rs1 31..26=26 25..20=56 14..12=5 6..2=0x04 1..0=3
-@zext.h rd rs1 31..25=4 24..20=0 14..12=4 6..2=0x0E 1..0=3
diff --git a/rv32_zbb b/rv32_zbb
new file mode 100644
index 0000000..cadea09
--- /dev/null
+++ b/rv32_zbb
@@ -0,0 +1,3 @@
+$pseudo_op rv_zbe::pack zext.h rd rs1 31..25=0x04 24..20=0 14..12=0x4 6..0=0x33
+$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x698 14..12=5 6..0=0x13
+$pseudo_op rv64_zbb::rori rori rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3
diff --git a/rv64_zbb b/rv64_zbb
new file mode 100644
index 0000000..fc19561
--- /dev/null
+++ b/rv64_zbb
@@ -0,0 +1,9 @@
+clzw rd rs1 31..20=0x600 14..12=1 6..2=0x06 1..0=3
+ctzw rd rs1 31..20=0x601 14..12=1 6..2=0x06 1..0=3
+cpopw rd rs1 31..20=0x602 14..12=1 6..2=0x06 1..0=3
+rolw rd rs1 rs2 31..25=0x30 14..12=1 6..2=0x0E 1..0=3
+rorw rd rs1 rs2 31..25=0x30 14..12=5 6..2=0x0E 1..0=3
+roriw rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x06 1..0=3
+rori rd rs1 31..26=0x18 shamt 14..12=5 6..2=0x04 1..0=3
+$pseudo_op rv64_zbe::packw zext.h rd rs1 31..25=0x04 24..20=0 14..12=0x4 6..2=0xE 1..0=0x3
+$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x6B8 14..12=5 6..0=0x13
diff --git a/opcodes-rv32zbb b/rv_zbb
index ed80dfe..9f384f6 100644
--- a/opcodes-rv32zbb
+++ b/rv_zbb
@@ -1,24 +1,15 @@
andn rd rs1 rs2 31..25=32 14..12=7 6..2=0x0C 1..0=3
orn rd rs1 rs2 31..25=32 14..12=6 6..2=0x0C 1..0=3
xnor rd rs1 rs2 31..25=32 14..12=4 6..2=0x0C 1..0=3
-
-rol rd rs1 rs2 31..25=48 14..12=1 6..2=0x0C 1..0=3
-ror rd rs1 rs2 31..25=48 14..12=5 6..2=0x0C 1..0=3
-
-rori rd rs1 31..26=24 shamt 14..12=5 6..2=0x04 1..0=3
-
clz rd rs1 31..20=0x600 14..12=1 6..2=0x04 1..0=3
ctz rd rs1 31..20=0x601 14..12=1 6..2=0x04 1..0=3
cpop rd rs1 31..20=0x602 14..12=1 6..2=0x04 1..0=3
-sext.b rd rs1 31..20=0x604 14..12=1 6..2=0x04 1..0=3
-sext.h rd rs1 31..20=0x605 14..12=1 6..2=0x04 1..0=3
-
-min rd rs1 rs2 31..25=5 14..12=4 6..2=0x0C 1..0=3
-minu rd rs1 rs2 31..25=5 14..12=5 6..2=0x0C 1..0=3
max rd rs1 rs2 31..25=5 14..12=6 6..2=0x0C 1..0=3
maxu rd rs1 rs2 31..25=5 14..12=7 6..2=0x0C 1..0=3
-
-orc.b rd rs1 31..26=10 25..20=7 14..12=5 6..2=0x04 1..0=3
-
-@rev8.rv32 rd rs1 31..26=26 25..20=24 14..12=5 6..2=0x04 1..0=3
-@zext.h.rv32 rd rs1 31..25=4 24..20=0 14..12=4 6..2=0x0C 1..0=3
+min rd rs1 rs2 31..25=5 14..12=4 6..2=0x0C 1..0=3
+minu rd rs1 rs2 31..25=5 14..12=5 6..2=0x0C 1..0=3
+sext.b rd rs1 31..20=0x604 14..12=1 6..2=0x04 1..0=3
+sext.h rd rs1 31..20=0x605 14..12=1 6..2=0x04 1..0=3
+rol rd rs1 rs2 31..25=0x30 14..12=1 6..2=0x0C 1..0=3
+ror rd rs1 rs2 31..25=0x30 14..12=5 6..2=0x0C 1..0=3
+$pseudo_op rv64_zbp::gorci orc.b rd rs1 31..20=0x287 14..12=0x5 6..0=0x13