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author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-07-14 23:04:56 -0700 |
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committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-07-27 00:15:26 -0700 |
commit | 0c0659e1866f04471d57b2dc678a11dd7da67576 (patch) | |
tree | 6eb50bc30203a80807f562102d21b2280986b109 | |
parent | cb1bca361f970ec0811413b451db612f81e1cd93 (diff) | |
download | riscv-opcodes-0c0659e1866f04471d57b2dc678a11dd7da67576.zip riscv-opcodes-0c0659e1866f04471d57b2dc678a11dd7da67576.tar.gz riscv-opcodes-0c0659e1866f04471d57b2dc678a11dd7da67576.tar.bz2 |
rvv: add whole ldst pseudo instruction and update reference link
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
-rw-r--r-- | opcodes-rvv | 2 | ||||
-rw-r--r-- | opcodes-rvv-pseudo | 5 |
2 files changed, 6 insertions, 1 deletions
diff --git a/opcodes-rvv b/opcodes-rvv index 14ad06d..a4c5e1a 100644 --- a/opcodes-rvv +++ b/opcodes-rvv @@ -61,7 +61,7 @@ vle32ff.v nf 28..26=0 vm 24..20=0x10 rs1 14..12=0x6 vd 6..0=0x07 vle64ff.v nf 28..26=0 vm 24..20=0x10 rs1 14..12=0x7 vd 6..0=0x07 # Vector Load/Store Whole Registers -# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#74-vector-unit-stride-instructions +# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#79-vector-loadstore-whole-register-instructions vl1re8.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 vl1re16.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 vl1re32.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 diff --git a/opcodes-rvv-pseudo b/opcodes-rvv-pseudo index b2857b5..6cf2bf4 100644 --- a/opcodes-rvv-pseudo +++ b/opcodes-rvv-pseudo @@ -1,2 +1,7 @@ # vmv1r.v, vmv2r.v, vmv4r.v, vmv8r.v @vmvnfr.v 31..26=0x27 25=1 vs2 simm5 14..12=0x3 vd 6..0=0x57 + +@vl1r.v 31..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +@vl2r.v 31..26=1 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 +@vl4r.v 31..26=3 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 +@vl8r.v 31..26=7 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 |