diff options
| author | Andrew Waterman <andrew@sifive.com> | 2024-08-27 17:14:38 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-08-27 17:14:38 -0500 |
| commit | 07b95c53a2585412f1a9044716445eb87af1e9d5 (patch) | |
| tree | 9d08fd4b382301748a7b0f32248edda9d40efc76 | |
| parent | 290792c1dd51cd23dacb12113f10567a9ede2a98 (diff) | |
| parent | 13be4eee8ad2402d41699cf733a2fc19d12593ba (diff) | |
| download | riscv-opcodes-07b95c53a2585412f1a9044716445eb87af1e9d5.zip riscv-opcodes-07b95c53a2585412f1a9044716445eb87af1e9d5.tar.gz riscv-opcodes-07b95c53a2585412f1a9044716445eb87af1e9d5.tar.bz2 | |
Merge pull request #278 from foss-for-synopsys-dwc-arc-processors/F/D/CSR_Pseudoinstructions
Added the rest of 1:1 PseudoInstructions
| -rw-r--r-- | rv_i | 4 | ||||
| -rw-r--r-- | rv_zicsr | 11 |
2 files changed, 14 insertions, 1 deletions
@@ -70,3 +70,7 @@ $pseudo_op rv_i::sltu snez rd rs2 31..25=0 19..15=0x0 14..12=3 6..2=0x0C 1..0= $pseudo_op rv_i::slt sltz rd rs1 31..25=0 24..20=0x0 14..12=2 6..2=0x0C 1..0=3 $pseudo_op rv_i::slt sgtz rd rs2 31..25=0 19..15=0x0 14..12=2 6..2=0x0C 1..0=3 +$pseudo_op rv_i::jalr jalr rs1 31..20=0 14..12=0 11..7=0x01 6..2=0x19 1..0=3 +$pseudo_op rv_i::jalr jr rs1 31..20=0 14..12=0 11..7=0x0 6..2=0x19 1..0=3 +$pseudo_op rv_i::jal jal jimm20 11..7=0x01 6..2=0x1b 1..0=3 +$pseudo_op rv_i::jal j jimm20 11..7=0x0 6..2=0x1b 1..0=3 @@ -1,6 +1,15 @@ -csrrw rd rs1 csr 14..12=1 6..2=0x1C 1..0=3 +csrrw rd rs1 csr 14..12=1 6..2=0x1C 1..0=3 csrrs rd rs1 csr 14..12=2 6..2=0x1C 1..0=3 csrrc rd rs1 csr 14..12=3 6..2=0x1C 1..0=3 csrrwi rd csr zimm 14..12=5 6..2=0x1C 1..0=3 csrrsi rd csr zimm 14..12=6 6..2=0x1C 1..0=3 csrrci rd csr zimm 14..12=7 6..2=0x1C 1..0=3 + +#pseudoinstructions +$pseudo_op rv_zicsr::csrrs csrr rd csr 19..15=0x0 14..12=2 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrw csrw rs1 csr 14..12=1 11..7=0x0 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs csrs rs1 csr 14..12=2 11..7=0x0 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrc csrc rs1 csr 14..12=3 11..7=0x0 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrwi csrwi csr zimm 14..12=5 11..7=0x0 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrsi csrsi csr zimm 14..12=6 11..7=0x0 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrci csrci csr zimm 14..12=7 11..7=0x0 6..2=0x1C 1..0=3 |