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| author | Andrew Waterman <andrew@sifive.com> | 2022-05-02 14:20:35 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-05-02 14:20:35 -0700 |
| commit | 36f37737b8241fca0e3a5a1d18555cb1d406cff8 (patch) | |
| tree | 11f8479f434fee1da06be155edeff0528c7026b7 /.gitignore | |
| parent | 71ecf3563997ea9e7e15a3295aecfe773ad9c04e (diff) | |
| parent | bc92b799d9e96b53a0e57e738bff8f12e6e1fc2d (diff) | |
| download | riscv-opcodes-36f37737b8241fca0e3a5a1d18555cb1d406cff8.zip riscv-opcodes-36f37737b8241fca0e3a5a1d18555cb1d406cff8.tar.gz riscv-opcodes-36f37737b8241fca0e3a5a1d18555cb1d406cff8.tar.bz2 | |
Merge branch 'migration-to-new-format' of https://github.com/incoresemi/riscv-opcodes into incoresemi-migration-to-new-formatincoresemi-migration-to-new-format
Diffstat (limited to '.gitignore')
| -rw-r--r-- | .gitignore | 6 |
1 files changed, 6 insertions, 0 deletions
@@ -5,3 +5,9 @@ inst.spinalhdl inst.go instr-table.tex priv-instr-table.tex +inst.rs +inst.spinalhdl +inst.sverilog +instr_dict.yaml + +__pycache__/ |