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BranchCommit messageAuthorAge
incoresemi-migration-to-new-formatMerge branch 'migration-to-new-format' of https://github.com/incoresemi/riscv...Andrew Waterman2 years
latex-based-output-refactorpre commit fixesIIITM-Jay3 days
masterMerge pull request #297 from huxuan0307/masterAndrew Waterman10 hours
riscv-bitmanipRemove subu.wAndrew Waterman4 years
rnmiAdd RNMI CSRs and instructionAndrew Waterman3 years
rvvFix config immsColin Schmidt6 years
vCSRRx is called ZicsrAndrew Waterman6 years
vadcUpdate encoding of vadc and friendsAndrew Waterman5 years
wfmiAdd wfmi instructionAndrew Waterman3 years
zfhAdd tentative RV32Zfh encodingAndrew Waterman5 years
[...]
 
 
AgeCommit messageAuthorFilesLines
2013-11-29Add vsetprec instructionconfprecQuan Nguyen1-0/+1
2013-11-24Merge branch 'master' into confprecQuan Nguyen5-59/+100
2013-11-24Add line in Makefile to parse confprecQuan Nguyen1-0/+1
2013-11-22add missing imm for storesYunsup Lee2-6/+7
2013-11-21fix slli/slliw encoding bugYunsup Lee4-7/+8
2013-10-29changes to the instr-tableYunsup Lee2-45/+85
2013-10-27Move half-precision opcodes to opcodes-hwacha-utQuan Nguyen3-41/+57
2013-10-27Merge branch 'master' of github.com:ucb-bar/riscv-opcodes into confprecQuan Nguyen1-0/+1
2013-10-18add gitignoreYunsup Lee1-0/+1
2013-10-17Add half-precision floating-point instructionsQuan Nguyen2-2/+44
[...]
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