1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
|
\chapter{``Zfh'' and ``Zfhmin'' Standard Extensions for Half-Precision Floating-Point,
Version 1.0}
This chapter describes the Zfh standard extension for 16-bit half-precision
binary floating-point instructions compliant with the IEEE 754-2008 arithmetic
standard.
The Zfh extension depends on the single-precision floating-point extension, F.
The NaN-boxing scheme described in Section~\ref{nanboxing} is extended to
allow a half-precision value to be NaN-boxed inside a single-precision value
(which may be recursively NaN-boxed inside a double- or quad-precision value
when the D or Q extension is present).
\begin{commentary}
This extension primarily provides instructions that consume half-precision
operands and produce half-precision results.
However, it is also common to compute on half-precision data using higher
intermediate precision.
Although this extension provides explicit conversion instructions that suffice
to implement that pattern, future extensions might further accelerate such
computation with additional instructions that implicitly widen their
operands---e.g., half$\times$half$+$single$\rightarrow$single---or implicitly
narrow their results---e.g., half$+$single$\rightarrow$half.
\end{commentary}
\section{Half-Precision Load and Store Instructions}
New 16-bit variants of LOAD-FP and STORE-FP instructions are added,
encoded with a new value for the funct3 width field.
\vspace{-0.2in}
\begin{center}
\begin{tabular}{M@{}R@{}F@{}R@{}O}
\\
\instbitrange{31}{20} &
\instbitrange{19}{15} &
\instbitrange{14}{12} &
\instbitrange{11}{7} &
\instbitrange{6}{0} \\
\hline
\multicolumn{1}{|c|}{imm[11:0]} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{width} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{opcode} \\
\hline
12 & 5 & 3 & 5 & 7 \\
offset[11:0] & base & H & dest & LOAD-FP \\
\end{tabular}
\end{center}
\vspace{-0.2in}
\begin{center}
\begin{tabular}{O@{}R@{}R@{}F@{}R@{}O}
\\
\instbitrange{31}{25} &
\instbitrange{24}{20} &
\instbitrange{19}{15} &
\instbitrange{14}{12} &
\instbitrange{11}{7} &
\instbitrange{6}{0} \\
\hline
\multicolumn{1}{|c|}{imm[11:5]} &
\multicolumn{1}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{width} &
\multicolumn{1}{c|}{imm[4:0]} &
\multicolumn{1}{c|}{opcode} \\
\hline
7 & 5 & 5 & 3 & 5 & 7 \\
offset[11:5] & src & base & H & offset[4:0] & STORE-FP \\
\end{tabular}
\end{center}
FLH and FSH are only guaranteed to execute atomically if the effective address
is naturally aligned.
FLH and FSH do not modify the bits being transferred; in particular, the
payloads of non-canonical NaNs are preserved.
FLH NaN-boxes the result written to {\em rd}, whereas FSH ignores all but
the lower 16 bits in {\em rs2}.
\section{Half-Precision Computational Instructions}
A new supported format is added to the format field of most
instructions, as shown in Table~\ref{tab:fpextfmth}.
\begin{table}[htp]
\begin{center}
\begin{tabular}{|c|c|l|}
\hline
{\em fmt} field &
Mnemonic &
Meaning \\
\hline
00 & S & 32-bit single-precision \\
01 & D & 64-bit double-precision \\
10 & H & 16-bit half-precision \\
11 & Q & 128-bit quad-precision \\
\hline
\end{tabular}
\end{center}
\caption{Format field encoding.}
\label{tab:fpextfmth}
\end{table}
The half-precision floating-point computational instructions are
defined analogously to their single-precision counterparts, but operate on
half-precision operands and produce half-precision results.
\vspace{-0.2in}
\begin{center}
\begin{tabular}{R@{}F@{}R@{}R@{}F@{}R@{}O}
\\
\instbitrange{31}{27} &
\instbitrange{26}{25} &
\instbitrange{24}{20} &
\instbitrange{19}{15} &
\instbitrange{14}{12} &
\instbitrange{11}{7} &
\instbitrange{6}{0} \\
\hline
\multicolumn{1}{|c|}{funct5} &
\multicolumn{1}{c|}{fmt} &
\multicolumn{1}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{rm} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{opcode} \\
\hline
5 & 2 & 5 & 5 & 3 & 5 & 7 \\
FADD/FSUB & H & src2 & src1 & RM & dest & OP-FP \\
FMUL/FDIV & H & src2 & src1 & RM & dest & OP-FP \\
FMIN-MAX & H & src2 & src1 & MIN/MAX & dest & OP-FP \\
FSQRT & H & 0 & src & RM & dest & OP-FP \\
\end{tabular}
\end{center}
\vspace{-0.2in}
\begin{center}
\begin{tabular}{R@{}F@{}R@{}R@{}F@{}R@{}O}
\\
\instbitrange{31}{27} &
\instbitrange{26}{25} &
\instbitrange{24}{20} &
\instbitrange{19}{15} &
\instbitrange{14}{12} &
\instbitrange{11}{7} &
\instbitrange{6}{0} \\
\hline
\multicolumn{1}{|c|}{rs3} &
\multicolumn{1}{c|}{fmt} &
\multicolumn{1}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{rm} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{opcode} \\
\hline
5 & 2 & 5 & 5 & 3 & 5 & 7 \\
src3 & H & src2 & src1 & RM & dest & F[N]MADD/F[N]MSUB \\
\end{tabular}
\end{center}
\section{Half-Precision Convert and Move Instructions}
New floating-point-to-integer and integer-to-floating-point conversion
instructions are added. These instructions are defined analogously to the
single-precision-to-integer and integer-to-single-precision conversion
instructions. FCVT.W.H or FCVT.L.H converts a half-precision floating-point
number to a signed 32-bit or 64-bit integer, respectively. FCVT.H.W or
FCVT.H.L converts a 32-bit or 64-bit signed integer, respectively, into a
half-precision floating-point number. FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and
FCVT.H.LU variants convert to or from unsigned integer values. FCVT.L[U].H and
FCVT.H.L[U] are RV64-only instructions.
\vspace{-0.2in}
\begin{center}
\begin{tabular}{R@{}F@{}R@{}R@{}F@{}R@{}O}
\\
\instbitrange{31}{27} &
\instbitrange{26}{25} &
\instbitrange{24}{20} &
\instbitrange{19}{15} &
\instbitrange{14}{12} &
\instbitrange{11}{7} &
\instbitrange{6}{0} \\
\hline
\multicolumn{1}{|c|}{funct5} &
\multicolumn{1}{c|}{fmt} &
\multicolumn{1}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{rm} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{opcode} \\
\hline
5 & 2 & 5 & 5 & 3 & 5 & 7 \\
FCVT.{\em int}.H & H & W[U]/L[U] & src & RM & dest & OP-FP \\
FCVT.H.{\em int} & H & W[U]/L[U] & src & RM & dest & OP-FP \\
\end{tabular}
\end{center}
New floating-point-to-floating-point conversion instructions are added. These
instructions are defined analogously to the double-precision
floating-point-to-floating-point conversion instructions.
FCVT.S.H or FCVT.H.S converts a half-precision floating-point number to
a single-precision floating-point number, or vice-versa, respectively.
If the D extension is present, FCVT.D.H or FCVT.H.D converts a half-precision
floating-point number to a double-precision floating-point number, or
vice-versa, respectively.
If the Q extension is present, FCVT.Q.H or FCVT.H.Q converts a half-precision
floating-point number to a quad-precision floating-point number, or
vice-versa, respectively.
\vspace{-0.2in}
\begin{center}
\begin{tabular}{R@{}F@{}R@{}R@{}F@{}R@{}O}
\\
\instbitrange{31}{27} &
\instbitrange{26}{25} &
\instbitrange{24}{20} &
\instbitrange{19}{15} &
\instbitrange{14}{12} &
\instbitrange{11}{7} &
\instbitrange{6}{0} \\
\hline
\multicolumn{1}{|c|}{funct5} &
\multicolumn{1}{c|}{fmt} &
\multicolumn{1}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{rm} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{opcode} \\
\hline
5 & 2 & 5 & 5 & 3 & 5 & 7 \\
FCVT.S.H & S & H & src & RM & dest & OP-FP \\
FCVT.H.S & H & S & src & RM & dest & OP-FP \\
FCVT.D.H & D & H & src & RM & dest & OP-FP \\
FCVT.H.D & H & D & src & RM & dest & OP-FP \\
FCVT.Q.H & Q & H & src & RM & dest & OP-FP \\
FCVT.H.Q & H & Q & src & RM & dest & OP-FP \\
\end{tabular}
\end{center}
Floating-point to floating-point sign-injection instructions, FSGNJ.H,
FSGNJN.H, and FSGNJX.H are defined analogously to the single-precision
sign-injection instruction.
\vspace{-0.2in}
\begin{center}
\begin{tabular}{R@{}F@{}R@{}R@{}F@{}R@{}O}
\\
\instbitrange{31}{27} &
\instbitrange{26}{25} &
\instbitrange{24}{20} &
\instbitrange{19}{15} &
\instbitrange{14}{12} &
\instbitrange{11}{7} &
\instbitrange{6}{0} \\
\hline
\multicolumn{1}{|c|}{funct5} &
\multicolumn{1}{c|}{fmt} &
\multicolumn{1}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{rm} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{opcode} \\
\hline
5 & 2 & 5 & 5 & 3 & 5 & 7 \\
FSGNJ & H & src2 & src1 & J[N]/JX & dest & OP-FP \\
\end{tabular}
\end{center}
Instructions are provided to move bit patterns between the floating-point and
integer registers.
FMV.X.H moves the half-precision value in floating-point register {\em rs1} to
a representation in IEEE 754-2008 standard encoding in integer register {\em
rd}, filling the upper XLEN-16 bits with copies of the floating-point number's
sign bit.
FMV.H.X moves the half-precision value encoded in IEEE 754-2008 standard
encoding from the lower 16 bits of integer register {\em rs1} to the
floating-point register {\em rd}, NaN-boxing the result.
FMV.X.H and FMV.H.X do not modify the bits being transferred; in particular,
the payloads of non-canonical NaNs are preserved.
\vspace{-0.2in}
\begin{center}
\begin{tabular}{R@{}F@{}R@{}R@{}F@{}R@{}O}
\\
\instbitrange{31}{27} &
\instbitrange{26}{25} &
\instbitrange{24}{20} &
\instbitrange{19}{15} &
\instbitrange{14}{12} &
\instbitrange{11}{7} &
\instbitrange{6}{0} \\
\hline
\multicolumn{1}{|c|}{funct5} &
\multicolumn{1}{c|}{fmt} &
\multicolumn{1}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{rm} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{opcode} \\
\hline
5 & 2 & 5 & 5 & 3 & 5 & 7 \\
FMV.X.H & H & 0 & src & 000 & dest & OP-FP \\
FMV.H.X & H & 0 & src & 000 & dest & OP-FP \\
\end{tabular}
\end{center}
\section{Half-Precision Floating-Point Compare Instructions}
The half-precision floating-point compare instructions are
defined analogously to their single-precision counterparts, but operate on
half-precision operands.
\vspace{-0.2in}
\begin{center}
\begin{tabular}{S@{}F@{}R@{}R@{}F@{}R@{}O}
\\
\instbitrange{31}{27} &
\instbitrange{26}{25} &
\instbitrange{24}{20} &
\instbitrange{19}{15} &
\instbitrange{14}{12} &
\instbitrange{11}{7} &
\instbitrange{6}{0} \\
\hline
\multicolumn{1}{|c|}{funct5} &
\multicolumn{1}{c|}{fmt} &
\multicolumn{1}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{rm} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{opcode} \\
\hline
5 & 2 & 5 & 5 & 3 & 5 & 7 \\
FCMP & H & src2 & src1 & EQ/LT/LE & dest & OP-FP \\
\end{tabular}
\end{center}
\section{Half-Precision Floating-Point Classify Instruction}
The half-precision floating-point classify instruction, FCLASS.H, is
defined analogously to its single-precision counterpart, but operates on
half-precision operands.
\vspace{-0.2in}
\begin{center}
\begin{tabular}{S@{}F@{}R@{}R@{}F@{}R@{}O}
\\
\instbitrange{31}{27} &
\instbitrange{26}{25} &
\instbitrange{24}{20} &
\instbitrange{19}{15} &
\instbitrange{14}{12} &
\instbitrange{11}{7} &
\instbitrange{6}{0} \\
\hline
\multicolumn{1}{|c|}{funct5} &
\multicolumn{1}{c|}{fmt} &
\multicolumn{1}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{rm} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{opcode} \\
\hline
5 & 2 & 5 & 5 & 3 & 5 & 7 \\
FCLASS & H & 0 & src & 001 & dest & OP-FP \\
\end{tabular}
\end{center}
\section{``Zfhmin'' Standard Extension for Minimal Half-Precision Floating-Point Support}
This section describes the Zfhmin standard extension, which provides minimal
support for 16-bit half-precision binary floating-point instructions.
The Zfhmin extension is a subset of the Zfh extension, consisting only
of data transfer and conversion instructions.
Like Zfh, the Zfhmin extension depends on the single-precision floating-point
extension, F.
The expectation is that Zfhmin software primarily uses the half-precision
format for storage, performing most computation in higher precision.
The Zfhmin extension includes the following instructions from the Zfh
extension: FLH, FSH, FMV.X.H, FMV.H.X, FCVT.S.H, and FCVT.H.S.
If the D extension is present, the FCVT.D.H and FCVT.H.D instructions are
also included.
If the Q extension is present, the FCVT.Q.H and FCVT.H.Q instructions are
additionally included.
\begin{commentary}
Zfhmin does not include the FSGNJ.H instruction, because it suffices to
instead use the FSGNJ.S instruction to move half-precision values between
floating-point registers.
\end{commentary}
\begin{commentary}
Half-precision addition, subtraction, multiplication, division, and
square-root operations can be faithfully emulated by converting the
half-precision operands to single-precision, performing the operation
using single-precision arithmetic, then converting back to
half-precision~\cite{roux:hal-01091186}.
Performing half-precision fused multiply-addition using this method incurs
a 1-ulp error on some inputs for the RNE and RMM rounding modes.
Conversion from 8- or 16-bit integers to half-precision can be emulated by
first converting to single-precision, then converting to half-precision.
Conversion from 32-bit integer can be emulated by first converting to
double-precision.
If the D extension is not present and a 1-ulp error under RNE or RMM is
tolerable, 32-bit integers can be first converted to single-precision instead.
The same remark applies to conversions from 64-bit integers without the Q
extension.
\end{commentary}
|