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[wavedrom, ,svg] .... {reg: [ {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB']}, {bits: 5, name: 'rd', attr: ['5','dest']}, {bits: 3, name: 'rm', attr: ['3','RM']}, {bits: 5, name: 'rs1', attr: ['5','src1']}, {bits: 5, name: 'rs2', attr: ['5','src2']}, {bits: 2, name: 'fmt', attr: ['2','S']}, {bits: 5, name: 'rs3', attr: ['5','src3']}, ]} ....