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//rv64i int-reg-reg
//### Integer Register-Register Operations
[wavedrom, ,svg]
....
{reg: [
{bits: 7, name: 'opcode', attr: 'OP', type: 8},
{bits: 5, name: 'rd', attr: 'dest', type: 2},
{bits: 3, name: 'func3', attr: ['SLL', 'SRL', 'SRA'], type: 8},
{bits: 5, name: 'rs1', attr: 'src1', type: 4},
{bits: 5, name: 'rs2', attr: 'src2', type: 4},
{bits: 7, name: 'funct7', attr: [0, 0, 32], type: 8}
]}
....
[wavedrom, ,svg]
....
{reg: [
{bits: 7, name: 'opcode', attr: 'OP-32', type: 8},
{bits: 5, name: 'rd', attr: 'dest', type: 2},
{bits: 3, name: 'func3', attr: ['ADDW', 'SLLW', 'SRLW', 'SUBW', 'SRAW'], type: 8},
{bits: 5, name: 'rs1', attr: 'src1', type: 4},
{bits: 5, name: 'rs2', attr: 'src2', type: 4},
{bits: 7, name: 'funct7', attr: [0, 0, 0, 32, 32], type: 8}
]}
....
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