1
2
3
4
5
6
7
8
9
10
11
|
[wavedrom, ,svg]
....
{reg: [
{bits: 7, name: 'opcode', attr: ['7', 'OP-IMM', 'OP-IMM', 'OP-IMM']},
{bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest']},
{bits: 3, name: 'funct3', attr: ['3', 'SLLI', 'SRLI', 'SRAI']},
{bits: 5, name: 'rs1', attr: ['5', 'src', 'src', 'src']},
{bits: 6, name: 'imm[5:0]', attr: ['6', 'shamt[5:0]', 'shamt[5:0]', 'shamt[5:0]']},
{bits: 6, name: 'imm[11:6]', attr: ['6', '000000', '000000', '010000']}
]}
....
|
