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//rv64i-addiw
[wavedrom, ,svg]
....
{reg: [
{bits: 7, name: 'opcode', attr: 'OP-IMM', type: 8},
{bits: 5, name: 'rd', attr: 'dest', type: 2},
{bits: 3, name: 'func3', attr: ['SLLI', 'SRLI', 'SRAI'], type: 8},
{bits: 5, name: 'rs1', attr: 'src', type: 4},
{bits: 6, name: 'imm[5:0]', attr: 'shamt[5:0]', type: 3},
{bits: 6, name: 'imm[11:6]', attr: [0, 0, 32], type: 8}
]}
....
[wavedrom, ,svg]
....
{reg: [
{bits: 7, name: 'opcode', attr: 'OP-IMM-32', type: 8},
{bits: 5, name: 'rd', attr: 'dest', type: 2},
{bits: 3, name: 'func3', attr: ['SLLIW', 'SRLIW', 'SRAIW'], type: 8},
{bits: 5, name: 'rs1', attr: 'src', type: 4},
{bits: 5, name: 'imm[4:0]', attr: 'shamt[4:0]', type: 3},
{bits: 1, name: '[5]', attr: 0},
{bits: 6, name: 'imm[11:6]', attr: [0, 0, 32], type: 8}
]}
....
|
