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//### Integer Register-Register Operations
[wavedrom, ,]
....
{reg: [
{bits: 7, name: 'opcode', attr: ['OP', 'OP', 'OP', 'OP'], type: 8},
{bits: 5, name: 'rd', attr: ['dest', 'dest', 'dest','dest'], type: 2},
{bits: 3, name: 'funct3', attr: ['ADD/SLT[U]', 'AND/OR/XOR', 'SLL/SRL', 'SUB/SRA'], type: 8},
{bits: 5, name: 'rs1', attr: ['src1', 'src1', 'src1', 'src1'], type: 4},
{bits: 5, name: 'rs2', attr: ['src2', 'src2', 'src2', 'src2'], type: 4},
{bits: 7, name: 'funct7', attr: [0, 0, 0, 0, 0, 0, 0, 0, 32, 32], type: 8}
]}
....
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