aboutsummaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)AuthorFilesLines
2024-05-08Matching Alasdair's changes.sail-inclusion-examplewmat2-1/+1
Matching Alasdair's changes.
2024-05-08Applying alasdairs fixeswmat2-2/+3
Applying alasdairs fixes
2024-05-08Fixing sail inclusion.wmat3-5/+6
Fixing sail inclusion.
2024-05-08Added alasdair's examples.wmat3-0/+15
Added sail inclusion examples.
2024-05-06Adding a directory and the sail index.wmat1-0/+111655
Adding a directory to hold the sail index and adding a generated index file to demonstrate sail inclusion in the spec. This may not be the final solution for this but will suffice for an example.
2024-05-03Update supervisor.adoc (#1382)riscv-isa-release-87edab7-2024-05-04Kersten Richter1-2/+2
https://github.com/riscv/riscv-isa-manual/issues/1370 Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-02Integrate Zicfilp and Zicfiss extension specs (#1380)Ved Shanbhogue18-435/+1607
- Updates CSR, Machine, Supervisor and Hypervisor chapters - Adds CFI chapter to Priv. and Unpriv.
2024-05-02Merge pull request #1378 from riscv/kersten1-patch-2riscv-isa-release-ed61a8d-2024-05-02Kersten Richter1-14/+8
Update to PMP R, W, and X bits
2024-05-02Update pmpcfg.adocKersten Richter1-1/+0
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-02Update pmpcfg.adocKersten Richter1-6/+7
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-02Update pmpcfg.adocKersten Richter1-6/+6
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-02Update pmpcfg.adocKersten Richter1-12/+6
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-02Update pmpcfg.adocKersten Richter1-6/+6
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-02Update pmpcfg.adocKersten Richter1-1/+1
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-02Update src/images/bytefield/pmpcfg.adocKersten Richter1-1/+1
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-02Update src/images/bytefield/pmpcfg.adocKersten Richter1-1/+1
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-02Update src/images/bytefield/pmpcfg.adocKersten Richter1-1/+1
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-02Update src/images/bytefield/pmpcfg.adocKersten Richter1-1/+1
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-02Update src/images/bytefield/pmpcfg.adocKersten Richter1-1/+1
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-02Update src/images/bytefield/pmpcfg.adocKersten Richter1-1/+1
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-02Update src/smcntrpmf.adocKersten Richter1-1/+1
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-05-01wordsmithingAndrew Waterman1-1/+1
2024-05-01Clarify EBREAK behavior applies in absence of debug moduleAndrew Waterman1-2/+3
2024-05-01Clarify that CSR implicit write ordering rule isn't specific to incrementsAndrew Waterman1-1/+2
See https://github.com/riscv/riscv-debug-spec/issues/1026#issuecomment-2088872276
2024-04-30Update src/images/bytefield/pmpcfg.adocKersten Richter1-1/+1
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-04-30Update src/images/bytefield/pmpcfg.adocKersten Richter1-1/+1
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-04-30Update src/images/bytefield/pmpcfg.adocKersten Richter1-1/+1
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-04-30Update src/images/bytefield/pmpcfg.adocKersten Richter1-1/+1
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-04-30Update pmpcfg.adocKersten Richter1-4/+4
Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-04-30Update pmpcfg.adocKersten Richter1-6/+6
errors Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-04-30Update pmpcfg.adocKersten Richter1-0/+6
fixing errors Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-04-30Update smcntrpmf.adocKersten Richter1-1/+1
To get rid of error Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-04-30Update pmpcfg.adocKersten Richter1-7/+1
Making the change that Andrew suggested in https://github.com/riscv/riscv-isa-manual/pull/909 Signed-off-by: Kersten Richter <kersten@riscv.org>
2024-04-29Merge pull request #1373 from riscv/1372-chapter-71-issuesriscv-isa-release-903996c-2024-04-29Bill Traynor1-2/+2
2024-04-29Update smcdeleg.adoc (#1375)riscv-isa-release-704d8a6-2024-04-29Beeman Strong1-2/+1
Minor text tweak Signed-off-by: Beeman Strong <97133824+bcstrongx@users.noreply.github.com>
2024-04-29Update smcntrpmf.adocBeeman Strong1-2/+2
Minor text improvements Signed-off-by: Beeman Strong <97133824+bcstrongx@users.noreply.github.com>
2024-04-29Fixing italics issue. (#1371)riscv-isa-release-0965a03-2024-04-29Bill Traynor1-3/+3
Fixes issue #1367 setting register name as monospaced in non-normative text and italicizing and bolding the trailing variable.
2024-04-26Don't hyphenate "sign extension" when used as nounAndrew Waterman6-12/+12
2024-04-26Fix inconsistent formattingAndrew Waterman1-1/+1
2024-04-26Fix unintended indentationAndrew Waterman1-0/+1
2024-04-25Add Zabha standard extension (#1364)Ved Shanbhogue2-0/+69
2024-04-25Update layout and fix broken citations (#1365)Ved Shanbhogue1-8/+11
2024-04-24Move BF16 chapter to more logical placeAndrew Waterman1-1/+1
Resolves #1362
2024-04-24RNMI clarificationAndrew Waterman1-1/+1
Needed because of 1153db082b34950dc282bc9b87727199c005c3ad
2024-04-24Merge pull request #1293 from riscv/kersten1-patch-2riscv-isa-release-a6ecaa1-2024-04-24Kersten Richter1-4/+6
Old PR - Add initial value of Figure A.13
2024-04-23Merge pull request #1357 from riscv/kersten1-patch-4riscv-isa-release-aa0572c-2024-04-24Kersten Richter2-44/+44
More register name clean up
2024-04-23Merge pull request #1359 from riscv/bfloat16riscv-isa-release-4d427c1-2024-04-23Ken Dockser2-0/+779
Bfloat16 - added chapter
2024-04-23Added mandatory space before forced page breakkdockser1-1/+6
2024-04-23Added back new-pages after each instructionkdockser1-5/+5
2024-04-23Clarify a possible RNMI exception trap handler configurationAndrew Waterman1-0/+3