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author | wmat <wmat@riscv.org> | 2024-05-08 11:19:39 -0400 |
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committer | wmat <wmat@riscv.org> | 2024-05-08 11:19:39 -0400 |
commit | dbe385f59ccaadab43008f5b649b085c09e6d684 (patch) | |
tree | 4f669db18e34924ba482cc4dbf25b020d369dffd /src | |
parent | aab233c2a46ad0f560617562305bf2d2283712d0 (diff) | |
download | riscv-isa-manual-sail-inclusion-example.zip riscv-isa-manual-sail-inclusion-example.tar.gz riscv-isa-manual-sail-inclusion-example.tar.bz2 |
Matching Alasdair's changes.sail-inclusion-example
Matching Alasdair's changes.
Diffstat (limited to 'src')
-rw-r--r-- | src/c-st-ext.adoc | 1 | ||||
-rw-r--r-- | src/rv64.adoc | 1 |
2 files changed, 1 insertions, 1 deletions
diff --git a/src/c-st-ext.adoc b/src/c-st-ext.adoc index dcf4ca6..268f5b4 100644 --- a/src/c-st-ext.adoc +++ b/src/c-st-ext.adoc @@ -310,7 +310,6 @@ only valid when _rd_≠x0 the code points with _rd_=x0 are reserved. C.LWSP SAIL Code: -//include::sail:execute[part=body,unindent,clause="RISCV_C_LWSP(_, _)"] sail::execute[clause="C_LWSP(_, _)",part=body,unindent] C.LDSP is an RV64C/RV128C-only instruction that loads a 64-bit value diff --git a/src/rv64.adoc b/src/rv64.adoc index 816594d..7b3c8dd 100644 --- a/src/rv64.adoc +++ b/src/rv64.adoc @@ -86,6 +86,7 @@ _imm[5] ≠ 0_ are reserved. sail::execute[part=body,dedent,clause="SHIFTIWOP(_,_,_,_)"] + [NOTE] ==== Previously, SLLIW, SRLIW, and SRAIW with _imm[5] ≠ 0_ |