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2021-09-14Merge branch 'Svnapot' into SvpbmtSvpbmtDaniel Lustig1-53/+48
2021-09-14Address first round of arch review feedbackDaniel Lustig1-8/+5
2021-09-14Some cosmetic rearrangement for arch reviewSvnapotDaniel Lustig1-53/+48
2021-08-30Merge branch 'Svnapot' into SvpbmtDaniel Lustig1-6/+1
2021-08-30Fix missing case in PBMT memory ordering.Daniel Lustig1-2/+3
2021-08-30Fix typo, and remove page/access fault explanationDaniel Lustig1-6/+1
2021-08-22Some cosmetic tweaksDaniel Lustig1-16/+19
2021-08-22Merge branch 'Svnapot' into SvpbmtDaniel Lustig1-25/+25
2021-08-22Some cosmetic reformattingDaniel Lustig1-25/+25
2021-08-06Clarify Svpbmt non-leaf PTEs and other wordingDaniel Lustig1-7/+13
2021-07-21Merge branch 'Svnapot' into SvpbmtDaniel Lustig1-14/+6
2021-07-21Clarify that N remains reserved under Sv39/48/57Daniel Lustig1-8/+5
2021-07-15Merge branch 'Svnapot' into SvpbmtDaniel Lustig1-2/+2
2021-07-15Merge branch 'virtual-memory' into SvnapotDaniel Lustig1-2/+2
2021-07-15Take "vice versa" back out from SFENCE definition.Daniel Lustig1-2/+2
2021-07-08Merge branch 'Svnapot' into SvpbmtDaniel Lustig1-1/+1
2021-07-08A few wording updatesDaniel Lustig1-40/+29
2021-07-08Fix off-by-one errorDaniel Lustig1-1/+1
2021-06-13First draft of SvpbmtDaniel Lustig1-20/+145
2021-06-02Merge branch 'virtual-memory' into SvnapotDaniel Lustig1-55/+36
2021-06-02Merge branch 'master' into virtual-memoryDaniel Lustig1-9/+11
2021-06-02Remove the "C" bit, per virt mem TG voteDaniel Lustig1-46/+23
2021-05-23Fix hyphenationAndrew Waterman1-1/+1
2021-05-17Fix typoDaniel Lustig1-1/+1
2021-05-17Typo and clarificationDaniel Lustig1-3/+4
2021-04-23Minor mstatus and sstatus layout edits. (#642)Steven Bellock1-9/+9
2021-04-23Resolve inconsistency regarding C and N bitsDaniel Lustig1-13/+12
2021-04-23Merge branch 'virtual-memory' into SvnapotDaniel Lustig1-15/+29
2021-04-21SUM should be hardwired to 0 for cores without paging (#641)Andrew Waterman1-0/+2
2021-03-08Clarify PA zero-extension rulesDaniel Lustig1-2/+14
2021-03-03Reserved PTE encodings also trigger page faultsDaniel Lustig1-3/+3
2021-03-03Reserved PTE bits cause page faultsDaniel Lustig1-5/+5
2021-02-24Reword over-SFENCE'ing commentaryDaniel Lustig1-4/+7
2021-02-23Reword text about SFENCE.VMA with invalid VADaniel Lustig1-8/+7
2021-02-21Add Svnapot Extension v0.1Daniel Lustig1-18/+169
2021-02-21Add Sv57 and Sv57x4 in the expected wayDaniel Lustig1-7/+148
2021-02-21Remove Svnapot from this branchDaniel Lustig1-177/+15
2021-02-21SFENCE.VMA with invalid rs1 has no effect.Daniel Lustig1-0/+8
2021-02-08Recommend tight sequences of SFENCE.VMAsDaniel Lustig1-0/+32
2021-02-02Rename Zsn to SvnapotDaniel Lustig1-5/+5
2021-01-14Implicit PTE accesses are performed at PTE widthDaniel Lustig1-0/+11
2021-01-14Relabel ZsnDaniel Lustig1-3/+3
2021-01-14Minor commentary tweakDaniel Lustig1-4/+5
2021-01-06More assorted translation and Zsn updatesDaniel Lustig1-18/+34
2020-12-08More small edits, thanks to @gfavor suggestionsDaniel Lustig1-5/+7
2020-11-20Clarify the behavior when reserved bits are setDaniel Lustig1-4/+12
2020-11-17One more clarifying sentence, thanks to @gfavorDaniel Lustig1-1/+3
2020-11-17One more tiny updateDaniel Lustig1-1/+1
2020-11-17Address feedback from @gfavorDaniel Lustig1-9/+14
2020-11-13Fix Table 4.5Daniel Lustig1-14/+15
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