| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2018-11-06 | Bumped base I version number to 2.1 to reflect ratified memory model, exclusi... | Krste Asanovic | 1 | -1/+1 |
| 2018-10-29 | Clarify that most integer instructions operate on XLEN bits in RV64 | Andrew Waterman | 1 | -0/+1 |
| 2018-08-06 | Cleaned up RV64 chapter to remove platform-specific mandates. | Krste Asanovic | 1 | -8/+11 |
| 2018-08-06 | Moved CSR instructions into separate chapter. | Krste Asanovic | 1 | -8/+0 |
| 2018-07-15 | More work on HINTs | Andrew Waterman | 1 | -0/+54 |
| 2018-07-15 | Fix spelling of "pseudoinstruction" | Andrew Waterman | 1 | -1/+1 |
| 2018-01-23 | Standardized on pseudoinstruction. | Krste Asanovic | 1 | -2/+2 |
| 2017-02-01 | Reorganize directory structure | Andrew Waterman | 1 | -0/+253 |
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index : riscv-isa-manual.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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