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riscv-isa-manual.git
1437-update-generated-filenames-to-be-more-desciptive
1454-fix-merge-and-release-workflow
1532-lack-of-list-of-figures-tables
Sv57
Svinval
Svnapot
Svpbmt
antora-refactor
aswaterman-patch-1
atomics-wording-v2
bonzini-hpmdelta
cnop
convert2adoc_rvwmo
csr-wip
dev/beeman/smctr-ssctr
fix-adoc-IDs
hypervisor
kersten1-patch-3
latex
lrsc
main
misa-ztso
msip
mtime-optional
n-ext
pmp
ratified-priv-v1.11-sans-hypervisor-draft
sail-inclusion-example
sfence-asid
smpmpmt
svkt
tmp
trap
v20240411
virtual-memory
wfmi
zam
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ztso-ratification
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priv-preface.tex
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Author
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2019-07-20
Isolate N extension into its own chapter in the priv spec
n-ext
Andrew Waterman
1
-0
/
+1
2019-06-21
Fix preface style
Andrew Waterman
1
-2
/
+2
2019-06-21
Add mstatush to preface
Andrew Waterman
1
-0
/
+2
2019-06-19
Add endianness control proposal to priv spec
Andrew Waterman
1
-0
/
+1
2019-06-16
Bump priv spec to v1.12-draft
Andrew Waterman
1
-4
/
+38
2019-06-08
Added text to indicate this is the ratified 1.11 version of the spec.
Ratified-IMFDQC-and-Priv-v1.11
Krste Asanovic
1
-4
/
+5
2019-04-11
forgot to bump hypervisor spec draft version
Andrew Waterman
1
-1
/
+1
2019-03-26
Add preface entry for mcountinhibit CSR
Andrew Waterman
1
-0
/
+2
2019-03-12
Specify synchronous exception priority ordering
Andrew Waterman
1
-0
/
+1
2019-03-07
Update preface
Andrew Waterman
1
-0
/
+1
2019-03-07
Add software constraint for future global-ASID extension
Andrew Waterman
1
-0
/
+4
2018-12-02
Remove PLIC chapter from privileged spec
Andrew Waterman
1
-0
/
+1
2018-12-02
Update privileged preface
Andrew Waterman
1
-2
/
+23
2018-12-02
Clarify misaligned-AMO emulation scheme
Andrew Waterman
1
-3
/
+1
2018-11-30
Update preface
Andrew Waterman
1
-0
/
+2
2018-09-23
Unused PMP fields are WARL 0, not WIRI
Andrew Waterman
1
-0
/
+1
2018-09-23
unused mip fields are wpri instead of wiri
Andrew Waterman
1
-0
/
+1
2018-09-23
unused misa fields are wlrl, not wiri
Andrew Waterman
1
-0
/
+1
2018-08-09
Added specification that xRET instructions may, but are not
Krste Asanovic
1
-1
/
+3
2018-04-13
Add preface entry
Andrew Waterman
1
-0
/
+1
2018-04-03
Specify coarser-than-4-byte PMP semantics
Andrew Waterman
1
-0
/
+1
2018-03-21
John Hauser's alternative writable-misa.C proposal
Andrew Waterman
1
-0
/
+2
2017-12-12
Describe optional support for misaligned AMOs (#117)
Andrew Waterman
1
-0
/
+3
2017-12-11
Fix xIE descriptive error
Andrew Waterman
1
-0
/
+2
2017-12-06
Constrain all harts to use same A/D-bit management scheme
Andrew Waterman
1
-0
/
+1
2017-11-09
Make MPP/SPP WARL fields
Andrew Waterman
1
-0
/
+1
2017-11-09
Add hypervisor draft proposal
Andrew Waterman
1
-0
/
+1
2017-11-09
fix typos
Andrew Waterman
1
-2
/
+2
2017-06-05
Add preface entry
Andrew Waterman
1
-1
/
+2
2017-06-03
Add preface entry for SUM change
Andrew Waterman
1
-0
/
+2
2017-06-03
Incorporate Allen's feedback
Andrew Waterman
1
-0
/
+13
2017-05-16
Fix typo in change log
Megan Wachs
1
-1
/
+1
2017-05-07
user spec -> 2.2; priv spec -> 1.10
Andrew Waterman
1
-1
/
+1
2017-05-07
Remove SBI chapter
Andrew Waterman
1
-0
/
+2
2017-05-07
Add missing preface note
Andrew Waterman
1
-0
/
+2
2017-05-06
Clarified expected use of XS to summarize additional extension
Krste Asanovic
1
-0
/
+2
2017-05-05
Attempt to explain SEIP discipline
Andrew Waterman
1
-0
/
+2
2017-04-11
SPTBR -> SATP
Andrew Waterman
1
-2
/
+4
2017-03-29
Add PMP to preface
Andrew Waterman
1
-0
/
+1
2017-03-28
Renamed mbadbits to mtval (for "Trap Value") to be more generic name for regi...
Krste Asanovic
1
-1
/
+1
2017-03-28
Add preface entry for page fault cause renumbering
Andrew Waterman
1
-0
/
+4
2017-03-26
Replaced mbadaddr with mbadbits register, which can now capture bad
Krste Asanovic
1
-0
/
+4
2017-03-21
Added rationale for removal of machine-mode base-and-bounds schemes for now.
Krste Asanovic
1
-2
/
+9
2017-03-20
Changed mvendorid to hold the JEDEC manufacturer code for the core vendor as ...
Krste Asanovic
1
-2
/
+5
2017-03-20
Now mideleg /medeleg only exist if lower privilege mode exists and can take t...
Krste Asanovic
1
-0
/
+3
2017-03-20
Removed explicit convention on shadow CSRs.
Krste Asanovic
1
-3
/
+5
2017-03-20
Add changelog entries for PUM -> SUM and MXR
Andrew Waterman
1
-0
/
+3
2017-03-19
fix typo
Andrew Waterman
1
-2
/
+2
2017-03-19
Excised H-mode from spec.
Krste Asanovic
1
-12
/
+18
2017-03-19
Fixed up licence and contributor details on front page.
Krste Asanovic
1
-2
/
+6
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