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riscv-isa-manual.git
1437-update-generated-filenames-to-be-more-desciptive
1454-fix-merge-and-release-workflow
1532-lack-of-list-of-figures-tables
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aswaterman-patch-1
atomics-wording-v2
bonzini-hpmdelta
cnop
convert2adoc_rvwmo
csr-wip
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hypervisor
kersten1-patch-3
latex
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misa-ztso
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pmp
ratified-priv-v1.11-sans-hypervisor-draft
sail-inclusion-example
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priv-csrs.tex
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2019-08-21
Use RV32 consistently in the CSR listing
Columbus240
1
-12
/
+12
2019-08-21
Remove trailing whitespace from priv-csrs.tex
Columbus240
1
-34
/
+34
2019-08-20
Fix typo in hcounteren privilege
Andrew Waterman
1
-1
/
+1
2019-08-16
hypervisor: add performance counter delta registers
Paolo Bonzini
1
-0
/
+5
2019-07-21
Move N extension into its own chapter in the priv spec
Andrew Waterman
1
-0
/
+1
2019-06-19
Add endianness control proposal to priv spec
Andrew Waterman
1
-0
/
+1
2019-06-16
Hypervisor v0.4 draft
Andrew Waterman
1
-14
/
+15
2019-04-05
Privileged Spec: Add dscratch0/1 to CSR listing (#361)
Philipp Wagner
1
-1
/
+2
2019-03-12
Reformat CSR address map table
Andrew Waterman
1
-29
/
+39
2019-01-21
Add hypervisor CSR listing
Andrew Waterman
1
-43
/
+42
2018-12-04
Debug registers 7A0-7AF are accessible to M-mode
Andrew Waterman
1
-3
/
+5
2018-12-04
Version of priv spec ready for ratification process
Andrew Waterman
1
-6
/
+10
2018-12-02
Non-standard -> custom
Andrew Waterman
1
-35
/
+23
2018-11-27
Misc. address translation clarifications
Andrew Waterman
1
-1
/
+1
2018-11-21
Add counter-inhibit mechanism
Andrew Waterman
1
-0
/
+1
2018-11-20
Fix colliding labels
Andrew Waterman
1
-3
/
+3
2018-09-23
No need for WIRI definition anymore
Andrew Waterman
1
-11
/
+0
2018-04-13
Remove hyphen from M-XLEN etc.
Andrew Waterman
1
-1
/
+1
2018-04-13
Clarifications re: writable XLEN
Andrew Waterman
1
-0
/
+28
2017-12-28
WIRI/WPRI fields should be hardwired to 0 (#121)
Andrew Waterman
1
-4
/
+8
2017-11-12
Clarify WLRL semantics
Andrew Waterman
1
-1
/
+1
2017-04-11
SPTBR -> SATP
Andrew Waterman
1
-1
/
+1
2017-03-30
Update PMP CSR listing
Andrew Waterman
1
-4
/
+8
2017-03-28
Renamed mbadbits to mtval (for "Trap Value") to be more generic name for regi...
Krste Asanovic
1
-4
/
+4
2017-03-26
Replaced mbadaddr with mbadbits register, which can now capture bad
Krste Asanovic
1
-4
/
+4
2017-03-20
Removed explicit convention on shadow CSRs.
Krste Asanovic
1
-16
/
+23
2017-03-19
Excised H-mode from spec.
Krste Asanovic
1
-40
/
+43
2017-02-26
Incorporate more Hauser feedback
Andrew Waterman
1
-10
/
+10
2017-02-21
Move counter-enable CSRs to trap-setup CSR space
Andrew Waterman
1
-9
/
+3
2017-02-20
mhcounteren -> mcounteren; mucounteren -> scounteren
Andrew Waterman
1
-3
/
+9
2017-02-01
Reorganize directory structure
Andrew Waterman
1
-0
/
+421