riscv-isa-manual.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Collapse)	Author	Files	Lines
2022-10-17	Rewrite Zam draft	Andrew Waterman	1	-1/+1

2022-08-29	Standardize on {\tt pc}, rather than PC	Andrew Waterman	1	-2/+2
	We were using a mix of the two, with a bias towards the former. Resolves #887
2022-07-07	Zmmul is ratified and is now version 1.0	Andrew Waterman	1	-0/+1

2022-01-09	Add Zihintntl spec (#810)	Andrew Waterman	1	-0/+1
	* Add NTLH draft * Second draft of NTLH * Incorporate Greg's feedback * rename NTLH to NTL Other HINTs don't end in H * Incorporate Krste's feedback * More Krste feedback * tweak * Address feedback from Josh and Greg * More Josh feedback * Change to use more common terms. (#653) Locally define "target instruction" term as a shorthand for the subsequent instruction to which the HINT applies. * Update to latest NTL proposal * rename NTL.LLC to NTL.ALL * Revisions from Krste * P2 -> PALL * Describe interaction of NTL and PREFETCH * Bump Zihintntl version Co-authored-by: Joshua Scheid <47677251+jscheid-ventana@users.noreply.github.com>
2022-01-07	Zhinxmin is ratified, too	Andrew Waterman	1	-1/+1
	Resolves #808
2022-01-06	Update version numbers for Zfh/Zfinx	Andrew Waterman	1	-5/+5

2021-08-02	Ratified Zihintpause is version 2.0	Andrew Waterman	1	-1/+1

2021-08-02	Fix format for ratified Zihintpause in preface table, part 2	John Hauser	1	-1/+1

2021-08-02	Fix format for ratified Zihintpause in preface table	John Hauser	1	-1/+1

2021-08-02	Zihintpause is ratified	John Hauser	1	-1/+1

2021-08-02	Update status of various extensions	John Hauser	1	-0/+15

2020-10-17	Add PAUSE instruction	Andrew Waterman	1	-0/+1

2020-07-22	Pmp wording fix (#545)	Stef O'Rear	1	-1/+1
	* Consistently use "access-fault exception" for PMPs Except for discussions of the xcause code itself which are "access fault". * Clarify behavior of locked TOR PMPs
2020-03-16	Add preface section for older version 20191213	Andrew Waterman	1	-0/+55
	Closes #491
2019-12-13	A extension v2.1 has been ratifiedRatified-IMAFDQC	Andrew Waterman	1	-1/+3

2019-07-23	Fix extension ordering in naming chapter and preface	Andrew Waterman	1	-3/+3

2019-07-21	Move N extension into its own chapter in the priv spec	Andrew Waterman	1	-1/+1

2019-06-24	Fix spelling	Andrew Waterman	1	-2/+2

2019-06-21	Changes to unprivileged spec for bi[g]-endian support	Andrew Waterman	1	-0/+7

2019-06-21	Bump version of unprivileged spec to 20190621-draft	Andrew Waterman	1	-0/+50

2019-06-08	Updated preface to indicate this is now ratified spec.	Krste Asanovic	1	-18/+18

2019-03-24	Improve CSR ordering section	Andrew Waterman	1	-2/+2
	h/t David Kruckemyer
2019-03-05	Version 20190305-Base-Ratification for ratification vote.	Krste Asanovic	1	-4/+9

2018-11-27	Add Hauser's definition of "memory access"	Andrew Waterman	1	-1/+1

2018-11-06	spelling20181106-Base-Ratification	Andrew Waterman	1	-1/+1

2018-11-06	Version ready for ratification process.	Krste Asanovic	1	-16/+11

2018-11-06	Updated status of counters. Not ready for ratification as there are issues ↵	Krste Asanovic	1	-1/+5
	outstanding.
2018-11-06	Allow access exceptions to be reported on misaligned atomic memory ↵	Krste Asanovic	1	-0/+2
	operations where they should not be emulated.
2018-11-06	Bumped base I version number to 2.1 to reflect ratified memory model, ↵	Krste Asanovic	1	-2/+6
	exclusion of fence.i, CSR instructions, and counters.
2018-11-06	Moved zifencetso back into main I chapter, as does not extend base ISA spec.	Krste Asanovic	1	-2/+0

2018-11-06	Gave CSR instruction module a name and a version, and made clear these are ↵	Krste Asanovic	1	-3/+4
	being ratified also.
2018-11-05	Merge branch 'master' of github.com:riscv/riscv-isa-manual	Krste Asanovic	1	-13/+13

2018-11-05	Update preface for unemulatable misaligned excpetions reported as access ↵	Krste Asanovic	1	-1/+2
	exception.
2018-11-05	tweaks	Andrew Waterman	1	-11/+11

2018-11-05	Fix spelling	Andrew Waterman	1	-2/+2

2018-11-04	Moved FENCE.I out of base I chapter into separate Zifencei chapter.	Krste Asanovic	1	-32/+47

2018-11-04	Made clear fence.tso is an optional extension	Krste Asanovic	1	-2/+2

2018-11-03	Removed text regarding big or bi-endian operation. For now, only specifying ↵	Krste Asanovic	1	-0/+2
	little-endian operation.
2018-08-28	F/D extensions to v2.2	Andrew Waterman	1	-2/+6

2018-08-26	Updated several "user" references to "unprivileged".	Krste Asanovic	1	-6/+7

2018-08-07	Made cleanup pass over floating-point extensions	Krste Asanovic	1	-1/+4

2018-08-07	Broke out actual perf counters into separate chapter.	Krste Asanovic	1	-1/+1

2018-08-06	Cleaned up RV64 chapter to remove platform-specific mandates.	Krste Asanovic	1	-0/+7

2018-08-05	Provide new description of misaligned load/store behavior compatible with ↵	Krste Asanovic	1	-1/+8
	privileged architecture.
2018-08-05	update preface.	Krste Asanovic	1	-1/+2

2018-07-06	Changes to intro as part of rationalizing ISA into ISA-only versus ↵	Krste Asanovic	1	-2/+7
	platform-mandates, and to make clearer there can be alternative privileged architectures.
2018-05-30	Hyphenate "instruction set" when it's part of a noun phrase	Andrew Waterman	1	-2/+2

2018-05-02	Tweaks to preface	Andrew Waterman	1	-3/+3

2018-05-02	Updates to the memory consistency model spec	Daniel Lustig	1	-3/+6
	This giant patch is the result of months of work from a lot of different people in the memory model TG.
2018-03-21	John Hauser's alternative writable-misa.C proposal	Andrew Waterman	1	-0/+2
	This one removes implementation-defined behavior but is still sane to implement.