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AgeCommit message (Expand)AuthorFilesLines
2021-08-11Clarify that RV64 accesses to mtime[cmp] are atomicAndrew Waterman1-1/+1
2021-08-11State that misa.F does not affect mstatus.FSAndrew Waterman1-2/+13
2021-08-06Clarify mepc invalid address conversionAndrew Waterman1-4/+6
2021-08-05Improve description of interrupt traps (#701)Andrew Waterman1-18/+18
2021-07-22Resolve contradiction in mtval definition (#685)Andrew Waterman1-7/+11
2021-07-22mstatush is not optional in priv-1.12 (#683)Andrew Waterman1-3/+0
2021-07-13Remove or downgrade more references to N extension (#674)John Hauser1-6/+5
2021-07-03CSR instead of field (#669)Iztok Jeras1-1/+1
2021-06-12Remove concept of hard reset from normative textAndrew Waterman1-1/+1
2021-06-08PMP RWX are collectively WARL, with R=0 W=1 being illegal (#658)Andrew Waterman1-3/+4
2021-06-04Remove T placeholder chapterAndrew Waterman1-1/+1
2021-06-03Remove L placeholder chapter from specAndrew Waterman1-1/+1
2021-05-25Use plural "base ISAs" rather than "base ISA" when appropriateAndrew Waterman1-1/+1
2021-04-23Minor mstatus and sstatus layout edits. (#642)Steven Bellock1-54/+53
2021-04-21SUM should be hardwired to 0 for cores without paging (#641)Andrew Waterman1-1/+1
2021-02-10Clarify type of timer interrupt (#617)Bartek Gąsiorzewski1-1/+1
2021-02-10Fix editing error introduced in 9ff515cd6695ac392e5ca32b73a135aa197e2778Andrew Waterman1-1/+1
2021-01-13Explain rationale for seting xPP=U on an xRETAndrew Waterman1-1/+7
2021-01-13Clean up NMI/mepc wordingAndrew Waterman1-2/+2
2021-01-12Additional FS clarificationAndrew Waterman1-1/+1
2021-01-12spell checkAndrew Waterman1-1/+1
2021-01-12clarify that FS need only be set to dirty if the state is actually changedAndrew Waterman1-0/+4
2020-12-22Make unused misa fields 0 (WARL) rather than WLRL. (#615)Paul Donahue1-1/+1
2020-11-19Dedicated section for machine-level memory-mapped registers (not standard CSR...Alexandre Joannou1-114/+116
2020-11-06PMP uses physical addresses (not effective addresses) (#610)Paul Donahue1-2/+2
2020-10-27mcounteren is WARLAndrew Waterman1-0/+4
2020-10-25PMP TOR clarificationsAndrew Waterman1-1/+8
2020-10-18Another attempt to clarify SEIP RMW semanticsAndrew Waterman1-4/+4
2020-10-17Attempt to clarify SEIP RMW semanticsAndrew Waterman1-4/+4
2020-10-13Both HWBPs and EBREAKs populate mtval (#601)Andrew Waterman1-1/+1
2020-10-06For emphasis, make MXR/SUM commentary normativeAndrew Waterman1-2/+0
2020-09-30Disabling and reenabling extensions makes their state unspecified (#585)Andrew Waterman1-0/+4
2020-09-29Clarify behavior when an extension is disabled (#592)gfavor1-0/+2
2020-09-28Clarify that "exception code" is used for both exceptions and interruptsAndrew Waterman1-1/+1
2020-09-01PMP changes don't need an sfence only when page-based virtual memory is not i...gfavor1-1/+1
2020-08-25Change "hardwired to other field" to "read-only field" (#571)John Hauser1-9/+9
2020-08-25Rename empty regions to vacant regions for consistency with unpriv specAndrew Waterman1-4/+4
2020-08-14Change "reserved for custom" to "designated for custom" (#566)John Hauser1-4/+4
2020-08-12mcounteren only exists if U-mode existsAndrew Waterman1-0/+2
2020-08-03Fix formatting of 2^XLENAndrew Waterman1-5/+5
2020-07-22Pmp wording fix (#545)Stef O'Rear1-4/+4
2020-07-17Remove redundant phrase from access-/page-fault textAndrew Waterman1-1/+1
2020-06-10Priority of misaligned load/store address checks is implementation-definedAndrew Waterman1-1/+18
2020-06-04Fix unclarity in MPRV definition introduced by 569d07195a8495460f04592d845515...Andrew Waterman1-1/+1
2020-05-22Extend PMP scheme to support 64 regionsAndrew Waterman1-27/+46
2020-05-05Clarify that _coherent_ main memory regions use RVWMO or RVTSOAndrew Waterman1-2/+4
2020-04-22Clarify that mtimecmp comparison is unsignedAndrew Waterman1-3/+4
2020-04-22Clarify that various reset events are relative to hart resetAndrew Waterman1-4/+4
2020-04-17Clarify that RV64 accesses to mtime/mtimecmp are atomicAndrew Waterman1-0/+3
2020-04-14Avoid "should" when describing a mandateAndrew Waterman1-2/+2
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