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instr-table.tex
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2022-01-21
Update Instruction Tables based on riscv-opcodes
Tsukasa OI
1
-236
/
+235
2021-07-28
Draft of Zfh extension for IEEE 754 binary16 support (#496)
Andrew Waterman
1
-2
/
+448
2021-03-15
Add FENCE.TSO and PAUSE to RV32I instruction table
Andrew Waterman
1
-0
/
+22
2019-05-14
zimm -> uimm in CSR instruction listing
Andrew Waterman
1
-3
/
+3
2019-03-05
Add Q opcode listing
Andrew Waterman
1
-0
/
+405
2018-11-20
Fix colliding labels
Andrew Waterman
1
-5
/
+0
2018-11-06
CSRRx is called Zicsr
Andrew Waterman
1
-1
/
+1
2018-11-06
Separate FENCE.I and CSRRx from RV32I table
Andrew Waterman
1
-179
/
+232
2018-08-27
Move out-of-date vector encoding to V chapter
Andrew Waterman
1
-735
/
+0
2018-08-25
Clarify that FENCE opcode bits aren't required to be 0
Andrew Waterman
1
-7
/
+5
2018-05-02
Updates to the memory consistency model spec
Daniel Lustig
1
-1
/
+1
2018-03-21
Add preliminary V encoding
Andrew Waterman
1
-0
/
+735
2017-05-07
SB/UJ -> B/J
Andrew Waterman
1
-2
/
+2
2017-04-14
Fix FMV.X.W/FMV.W.X in instruction listings
Andrew Waterman
1
-2
/
+2
2017-02-01
Reorganize directory structure
Andrew Waterman
1
-0
/
+1958