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2022-09-16More Hauser editszfbAndrew Waterman1-2/+2
2022-09-16Tighten description of FCVTMOD assembly syntaxAndrew Waterman1-2/+2
2022-09-16Tighten description of FCVTMOD exception behaviorAndrew Waterman1-1/+2
2022-09-16FROUND.NX -> FROUNDNXAndrew Waterman1-6/+6
The dots separate operands; we prefer not to use them to delineate words within the operator.
2022-09-16FCVT.MOD -> FCVTMODAndrew Waterman1-3/+3
The dots separate operands; we prefer not to use them to delineate words within the operator.
2022-09-16Reorder Zfa sections per Hauser's feedbackAndrew Waterman1-115/+119
2022-09-15Rename Zfb to Zfa at request of Zfbfmin authorsAndrew Waterman2-6/+6
...to avoid confusion between similar extension names.
2022-09-15Replace MAX with 16 in FLI; improve descriptionAndrew Waterman1-15/+24
2022-09-15rtz must be specified in FCVT.MOD.W.D instructionAndrew Waterman1-0/+5
2022-09-15Rename FCVT.JS.W.D to FCVT.MOD.W.DAndrew Waterman1-6/+7
2022-09-15Improve description of FCVT.JS.W.DAndrew Waterman1-2/+2
2022-09-15Improve FLI tableAndrew Waterman1-12/+12
2022-09-06Zfb also contains FLI.{H, S, D, Q}Andrew Waterman1-0/+91
2022-08-24Zfb also contains FCVT.JS.W.DAndrew Waterman1-0/+22
2022-08-19Zfb also contains FROUND[.NX]Andrew Waterman1-2/+37
2022-06-06Add draft of Zfb extensionAndrew Waterman2-0/+100
2022-04-04Fix BOOM URLAndrew Waterman1-1/+1
Resolves #833
2022-03-28Add note about FCVT.Q.L[U] never rounding (like FCVT.D.W[U])Andrew Waterman1-1/+2
2022-03-18Fix copy-paste errors in Sv57x4 descriptionAndrew Waterman1-4/+4
h/t @pperesse
2022-03-12improve description of store-conditional failure codes (#827)Andrew Waterman1-3/+3
2022-03-01Svpbmt cannot override vacant PMA regions. (#826)Paul Donahue1-0/+2
2022-03-01Update priv spec contributorsAndrew Waterman1-2/+2
2022-02-24Hypervisor: use HFENCE.GVMA after PMP write to synchronize ↵John Ingalls1-8/+5
VS-enabled-G-disabled (#797) * Hypervisor: use HFENCE.GVMA after PMP write to synchronize VS-enabled-G-disabled * specify synchronization with the guest's page tables only in the G-off case * from @aswaterman
2022-02-23Improve description of SvnapotAndrew Waterman1-6/+6
See #824
2022-02-22Zihintntl: fix chapter label (#821)Antony Pavlov1-1/+1
LaTeX produces this during build process: LaTeX Warning: Label `chap:zihintpause' multiply defined It looks like the `chap:zihintpause' label was copy-pasted from Zihintpause chapter. The commit sets appropriate label for the Zihintntl chapter. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
2022-02-17rocket-chip is hosted at chipsalliance, not freechipsprojectAndrew Waterman1-1/+1
2022-02-17Adds CV32E41P to MARCHID (#818)Ibrahim Abu Kharmeh1-0/+1
Adds [CV32E41P ]https://github.com/openhwgroup/cv32e41p to the MARCHID list. The core started its life as a fork of the CV32E40P core to implement the official RISC-V [Zfinx](https://github.com/riscv/riscv-zfinx/blob/main/zfinx-spec-20210511-0.41.pdf) and [Zce](https://github.com/riscv/riscv-code-size-reduction/releases/tag/V0.50.1-TOOLCHAIN-DEV) ISA extensions. Closes https://github.com/openhwgroup/cv32e41p/issues/7
2022-02-08Make FP conversion/move section names consistentAndrew Waterman2-2/+2
In F/D, the section is named "Conversion"; in Q/Zfh, it was named "Convert".
2022-01-25Update priv preface to reflect draft statusAndrew Waterman1-0/+32
2022-01-25misa.V means "V" vector extensionAndrew Waterman1-1/+1
This was ratified as part of the V extension's ratification.
2022-01-25Remove tentative purpose for reserved misa.B and misa.J bitsAndrew Waterman1-2/+2
This change has no normative effect. What were formerly informally referred to as the B and J extensions are instead going to become multiple smaller and disjoint extensions. Since it appears unlikely that B and J will ultimately have any meaning, simply mark these misa bits as "reserved", rather than "tentatively reserved for X".
2022-01-20Merge pull request #815 from a4lg/update-instr-table-20220121Andrew Waterman2-300/+306
Update Instruction Tables based on riscv-opcodes
2022-01-21Update Instruction Tables based on riscv-opcodesTsukasa OI2-300/+306
Now, the entire instruction tables are generated by riscv-opcodes. CMO instructions (Zicbo[mpz] extensions) are manually removed because they are not yet defined in the ISA Manual.
2022-01-19Merge pull request #813 from a4lg/riscv-hints-new-1-20220119Andrew Waterman3-14/+34
Refine HINT Instruction references (including tables)
2022-01-20Remove "no hints are defined" text in RVCTsukasa OI1-1/+1
Since we defined RVC hints (Zihintntl extension), we no longer need this text.
2022-01-20Add Zihintntl hints to HINT Instruction tablesTsukasa OI3-8/+28
Compressed design of non-temporal locality hints is chosen to fit all HINT instructions in RV64I to one page (as oversized tables can cause various problems).
2022-01-20Change compressed hint exampleTsukasa OI1-2/+2
Because `C.ADD x0, t0` DOES encode the same hint as `ADD x0, x0, t0` in Zihintntl extension (C.NTL.ALL and NTL.ALL), we need to change the example (`C.ADD x0, a0 [x10]` and `ADD x0, x0, a0 [x10]` are chosen considering simplicity and available space).
2022-01-20Replace semicolon with a colonTsukasa OI1-1/+1
This is a port of rv32.tex in commit ea9410a6a5ea ("Add PAUSE instruction") to c.tex.
2022-01-20Remove "no hints are defined" text in RV64ITsukasa OI1-2/+2
This is a port of rv32.tex in commit ea9410a6a5ea ("Add PAUSE instruction") to rv64.tex.
2022-01-15Zihintntl: Fix number of hint instruction variants (#812)Tsukasa #01 (a4lg)1-1/+1
2022-01-14hypervisor: Add Sv57 to &x4 address witdth list (#811)Dylan Reid1-1/+1
The Sv57 example wasn't included in the list of expanded widths for the *x4 modes. Signed-off-by: Dylan Reid <dgreid@rivosinc.com> Co-authored-by: Dylan Reid <dgreid@rivosinc.com>
2022-01-10Incorporate Kruckemyer's feedback on NTLAndrew Waterman1-6/+6
2022-01-10Clarify forbidden execution scenarios in A.1 litmus test (#809)Daniel Mangum1-1/+1
Updates description of forbidden execution where a0=1 in the figure A.1 litmus test by specifying that (c) reads the value written by (a) in both scenarios. Signed-off-by: hasheddan <georgedanielmangum@gmail.com>
2022-01-09fix formattingAndrew Waterman1-1/+1
2022-01-09Add Zihintntl spec (#810)Andrew Waterman3-0/+204
* Add NTLH draft * Second draft of NTLH * Incorporate Greg's feedback * rename NTLH to NTL Other HINTs don't end in H * Incorporate Krste's feedback * More Krste feedback * tweak * Address feedback from Josh and Greg * More Josh feedback * Change to use more common terms. (#653) Locally define "target instruction" term as a shorthand for the subsequent instruction to which the HINT applies. * Update to latest NTL proposal * rename NTL.LLC to NTL.ALL * Revisions from Krste * P2 -> PALL * Describe interaction of NTL and PREFETCH * Bump Zihintntl version Co-authored-by: Joshua Scheid <47677251+jscheid-ventana@users.noreply.github.com>
2022-01-09Clarify HLVX exception typesAndrew Waterman1-0/+4
2022-01-07Zhinxmin is ratified, tooAndrew Waterman1-1/+1
Resolves #808
2022-01-06Remove misleading text about MPRV for less-privileged modesAndrew Waterman1-3/+2
...since MPRV cannot be 1 in less-privileged modes any longer. Closes #807
2022-01-06Update version numbers for Zfh/ZfinxAndrew Waterman3-18/+7
2021-12-29Clarify handling of direct and indirect vsatp.MODE writes with Reserved values.gfavor1-4/+3
Clarify the intent to allow (but not require) the handling of writes to the vsatp.MODE field with Reserved values to be the same when performed by a hypervisor directly writing vsatp versus a guest OS writing vsatp indirectly via an satp write.
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