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2021-10-13Merge branch 'master' into virtual-memoryvirtual-memoryDaniel Lustig30-666/+2155
2021-10-05Fix editing error in mtval/stval definitionAndrew Waterman2-71/+53
2021-10-04Clarify order in which PMP CSRs must be implementedAndrew Waterman1-1/+2
2021-10-01Fix permissions of *envcfg CSRsAndrew Waterman1-3/+3
2021-09-30Improve description of FENCE.TSOAndrew Waterman1-5/+4
2021-09-21Add example to clarify mip.SEIP behaviorAndrew Waterman1-0/+8
2021-09-21Bump priv version numberAndrew Waterman1-1/+1
2021-09-15Priv-1.12 spec for public reviewriscv-privileged-20210915-public-reviewAndrew Waterman2-8/+7
2021-09-15JohnH is an editor of the priv specAndrew Waterman1-1/+1
2021-09-15RISC-V Foundation -> RISC-V InternationalAndrew Waterman6-12/+12
2021-09-15Freeze the hypervisor extension, version 1.0.0-rc (#739)John Hauser2-4/+7
2021-09-15mip.MSIP and mie.MSIE may be hardwired zeros (#738)John Hauser1-0/+4
2021-09-14Hypervisor extension requires page-based address translation (#737)John Hauser1-1/+2
2021-09-14Fix apparent typo re hpmcounter*h (#735)Scott Johnson1-1/+1
2021-09-14State behavior of uncacheable accesses to cacheable locationsAndrew Waterman1-0/+13
2021-09-14Clarify that WARL fields contain legal values after reset (#734)Andrew Waterman1-0/+1
2021-09-11Rename STCE to STCD to reverse its polarityAndrew Waterman2-4/+4
2021-09-10Generalize SSIP to support forthcoming interrupt controllers (#726)Andrew Waterman2-23/+4
2021-09-10Speculative implicit reads, v2 (#724)Andrew Waterman3-2/+18
2021-09-09Fix a typo in Figure A.13. (#733)Daniel Lustig1-1/+1
2021-09-08Merge pull request #727 from riscv/mseccfgAndrew Waterman5-2/+393
2021-09-08FIOM may be hardwired when satp is hardwiredAndrew Waterman2-1/+4
2021-09-05Make virtual instruction exceptions more consistent for VU mode (#730)John Hauser1-3/+13
2021-09-02Describe purpose of FIOM mechanismAndrew Waterman2-0/+45
2021-09-02Pedantically clarify behavior of writing lo/hi parts of countersAndrew Waterman1-4/+5
2021-09-01Remove errant preface entryAndrew Waterman1-1/+0
2021-09-01Clarify widths of privileged CSRs (#728)John Hauser3-44/+49
2021-09-01FIOM may optionally not exist in M/U systemsAndrew Waterman1-0/+2
2021-08-30Revert "Replace "EEI" with "execution environment" (#723)"Andrew Waterman4-49/+33
2021-08-30Fix constraint on existence of menvcfg[h]/FIOMAndrew Waterman1-2/+3
2021-08-29FIOM affects aq/rl, tooAndrew Waterman3-0/+16
2021-08-29Add henvcfg/senvcfg CSRsAndrew Waterman3-0/+165
2021-08-29Minor changes to JohnH's henvcfg specAndrew Waterman1-30/+36
2021-08-29Add *envcfg CSR allocationsAndrew Waterman1-0/+11
2021-08-29Add CSRs henvcfg/henvcfgh to hypervisor extensionJohn Hauser1-2/+88
2021-08-29Add mseccfg CSRAndrew Waterman3-0/+56
2021-08-29Add preface entryAndrew Waterman1-0/+2
2021-08-29Designate some of SYSTEM opcode for custom useAndrew Waterman1-0/+40
2021-08-28Add mconfigptr CSR (#697)Andrew Waterman3-0/+49
2021-08-28Replace "EEI" with "execution environment" (#723)John Hauser4-33/+49
2021-08-27Fix (again) non-normative CSR side-effect textAndrew Waterman1-2/+1
2021-08-25Remove historical remark on MRET definitionAndrew Waterman1-9/+0
2021-08-24Fix non-normative text about CSR ordering (#720)Andrew Waterman1-9/+12
2021-08-24Add marchid for Hummingbirdv2 E203 (#664)hucan71-1/+1
2021-08-18Update H chapter table of synchronous exception priorities (#717)John Hauser1-20/+19
2021-08-18Tweak table of synchronous exception priorities (#716)John Hauser1-5/+6
2021-08-17Make explicit the priorities of synch. exceptions of H extension (#711)John Hauser1-0/+53
2021-08-17Clarify priorities of synchronous exceptions (#715)John Hauser1-14/+30
2021-08-16stval already cannot be zero on breakpoints, misaligned addresses (#714)John Hauser1-5/+2
2021-08-16VS mode should not see exception code 10 (#712)John Hauser1-0/+1
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