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2018-11-27TMPtmpAndrew Waterman1-2/+26
2018-11-27Spell checkAndrew Waterman1-2/+2
2018-11-27Add Hauser's definition of "memory access"Andrew Waterman2-1/+56
2018-11-27Add commentary about MPRV and writable XLENAndrew Waterman1-0/+5
Closes #107
2018-11-27Extension XS fields might not be in mstatusAndrew Waterman1-1/+1
Fixes #64
2018-11-27Remove upper bound on stvec.MODE=Vectored alignment, like mtvecAndrew Waterman1-2/+1
2018-11-27Misc. address translation clarificationsAndrew Waterman4-21/+22
Courtesy @gameboo in #205
2018-11-27Clarification of ordering annotation semantics (#246)kdockser1-1/+3
* Clarification of ordering annotation semantics As discussed (and approved) in the weekly memory model meeting, this change is the sister of a similar change in the RVWMO chapter. In each case the intent is to clarify that these memory models are completely defined in this specification. More specifically, the axiomatic definitions of the annotations are sufficient and should be used instead of any other understanding of these terms. * Added links, corrected emdash * Tweaks to the commentary Reworded "programatically load" to "Subsequent (in program order)" - there is no need to specify this is the same hart as this is implicit in "program order". Likewise, there is no need to say "to the same address" as the store buffer would not forward to a different address. The point of specifying the Load Value Axiom, is to make it clear that it is the axiom that allows the expected TSO behavior, not the RCpc annotation.
2018-11-26Add Z-extensions to naming chapterAndrew Waterman1-4/+16
Closes #263.
2018-11-26Clarify that bits 16 and up of *ip/*ie are "custom"Andrew Waterman1-14/+18
Closes #271.
2018-11-26Clarify which instructions have RM field but don't use itAndrew Waterman1-3/+3
Closes #279
2018-11-26Add FENCE to HINT tableAndrew Waterman1-1/+2
2018-11-21Clarify that mtimecmp writes aren't synchronous with MTIP readsAndrew Waterman1-0/+12
2018-11-21note that xtval is written upon a trapAndrew Waterman1-1/+3
2018-11-21Add counter-inhibit mechanismAndrew Waterman2-0/+65
2018-11-21fix typosAndrew Waterman1-2/+2
2018-11-20Fix colliding labelsAndrew Waterman5-12/+4
h/t @pmundkur Resolves #278
2018-11-20Fix minor typos in the operational model. (#277)Prashanth Mundkur1-8/+8
2018-11-20Don't duplicate ECALL/EBREAK encodings between Vols. I and IIAndrew Waterman2-25/+3
Resolves #276
2018-11-19Remove comment about side effects on writesAndrew Waterman1-4/+3
Resolves #272
2018-11-16Improved wording.Krste Asanovic1-2/+2
2018-11-16Clarified that LR/SC forward progress guarantee might only hold for a subset ↵Krste Asanovic1-3/+5
of instruction and data memory space depending on execution environment.
2018-11-16Change funct to funct2 in the CA format (#262)Luís Marques1-2/+2
In the CA format, funct is changed to funct2, for consistency with the base ISA (which distinguishes between funct7 and funct3).
2018-11-16Clarified behavior of CSR instructions with respect to read and write side ↵Krste Asanovic1-4/+48
effects. Closed #267
2018-11-09WFI is not a HINTAndrew Waterman2-4/+3
2018-11-07Re-version spec to 20181221-Public-Review-draftAndrew Waterman1-1/+1
2018-11-07Register YARVI's machid (#260)Tommy Thorn1-0/+1
2018-11-07Describe the AMOs as "bitwise", not "logical" (#259)Palmer Dabbelt1-2/+2
"logical AND" usually means C's "&&" operator, not "&" operator. Thanks to Bodhisattva Debnath for pointing out the issue!
2018-11-07Update marchid.md (#256)Dmitri Pavlov1-0/+1
2018-11-07Update marchid.md for VectorBlox ORCA (#253)vbx-glemieux1-0/+1
2018-11-07Revert "Update marchid.md (#254)"Andrew Waterman1-2/+0
This reverts commit 327be43b7907645c6a63876f1064008dcfda1b43.
2018-11-07Update marchid.md (#254)Dmitri Pavlov1-0/+2
2018-11-06spelling20181106-Base-RatificationAndrew Waterman2-2/+2
2018-11-06Version ready for ratification process.Krste Asanovic2-17/+12
2018-11-06CSRRx is called ZicsrAndrew Waterman1-1/+1
2018-11-06Updated status of counters. Not ready for ratification as there are issues ↵Krste Asanovic3-5/+9
outstanding.
2018-11-06Update .gitignoreAndrew Waterman1-0/+1
2018-11-06Separate FENCE.I and CSRRx from RV32I tableAndrew Waterman1-179/+232
2018-11-06Define new RVC format CA; state that C.AND, etc. use itAndrew Waterman1-6/+14
This is not a functional change, just an improvement to the description. Resolves #45
2018-11-06mcycle counts cycles across the entire core, like rdcycleAndrew Waterman1-1/+2
Rationale is provided in the unprivileged manual (counters.tex). Resolves #249
2018-11-06Make pmaddr=FF..FF well-definedAndrew Waterman1-1/+1
2018-11-06Stated bytes are 8 bits and using IEC80000-13:2008Krste Asanovic1-1/+2
Closed #173
2018-11-06Allow access exceptions to be reported on misaligned atomic memory ↵Krste Asanovic2-10/+20
operations where they should not be emulated.
2018-11-06Bumped base I version number to 2.1 to reflect ratified memory model, ↵Krste Asanovic3-4/+8
exclusion of fence.i, CSR instructions, and counters.
2018-11-06Moved zifencetso back into main I chapter, as does not extend base ISA spec.Krste Asanovic4-80/+17
2018-11-06Gave CSR instruction module a name and a version, and made clear these are ↵Krste Asanovic2-4/+5
being ratified also.
2018-11-06Made clear that this is only the first standard calling convention.Krste Asanovic1-2/+11
2018-11-05Merge branch 'master' of github.com:riscv/riscv-isa-manualKrste Asanovic3-15/+16
2018-11-05Update preface for unemulatable misaligned excpetions reported as access ↵Krste Asanovic1-1/+2
exception.
2018-11-05Allowed certain un-emulatable misaligned accesses to be reported with access ↵Krste Asanovic1-7/+10
exceptions instead of address-misalignment exceptions.
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