TMPtmp

1 files changed, 26 insertions, 2 deletions

diff --git a/src/machine.tex b/src/machine.tex
index 539838f..2153eac 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -176,6 +176,17 @@ ISA observed at any level, and supports a much richer command
 interface without burdening hardware designs.
 \end{commentary}
 
+Unless {\tt misa} is hardwired to zero, the I and E bits are always
+complements of each other.  Hence, either both are read-only or both are
+writable.  If they are writable, then an attempt to set them to the same value
+{\em x} causes I to be set to {\em x} and E to be set to !{\em x}.
+
+The implementation may impose additional constraints on the collective setting
+of two or more {\tt misa} fields, in which case they function collectively as
+a single \warl\ field.  For example, an implementation might require that the
+D bit be clear unless the F bit is set.  An attempt to write an unsupported
+combination causes those bits to be set to some supported combination.
+
 Writing {\tt misa} may increase IALIGN, e.g., by disabling the ``C''
 extension.
 If an instruction that would write {\tt misa} increases IALIGN, and
@@ -699,8 +710,13 @@ hooks necessary to lazily populate shadow page tables.
 \end{commentary}
 
 The TW (Timeout Wait) bit supports intercepting the WFI instruction (see
-Section~\ref{wfi}).  When TW=0, the WFI instruction is permitted in S-mode.
-When TW=1, if WFI is executed in S-mode, and it does not complete within an
+Section~\ref{wfi}).  When TW=0, the TW mechanism does not inhibit the WFI
+instruction from executing in the next-lowest privileged mode (S-mode if
+implemented, else U-mode).
+
+When TW=1,
+then if WFI is executed in less-privileged modes, and it does not complete
+if WFI is executed in less-privileged modes, and it does not complete within an
 implementation-specific, bounded time limit, the WFI instruction causes an
 illegal instruction trap.  The time limit may always be 0, in which case WFI
 always causes an illegal instruction trap in S-mode when TW=1.
@@ -712,6 +728,14 @@ instruction can trigger a world switch to another guest OS, rather than
 wastefully idling in the current guest.
 \end{commentary}
 
+If S-mode is implemented, WFI is not valid in U-mode, irrespective of the
+setting of TW.
+
+\begin{commentary}
+A future extension might add a "don't trap wait" bit to {\tt sstatus}, so that
+S-mode could selectively permit execution of WFI in U-mode.
+\end{commentary}
+
 The TSR (Trap SRET) bit supports intercepting the supervisor exception return
 instruction, SRET.  When TSR=1, attempts to execute SRET while executing in
 S-mode will raise an illegal instruction exception.  When TSR=0, this