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AgeCommit message (Expand)AuthorFilesLines
2018-12-20Improve description of IEEE exception-flag settingAndrew Waterman1-10/+9
2018-12-20Add contributorAndrew Waterman1-1/+1
2018-12-20Clarify that PTE updates aren't atomic w.r.t. the ultimate access (#308)Andrew Waterman1-3/+9
2018-12-20Clarify sign extension of W and D instructions (#313)Bruce Hoult1-5/+7
2018-12-20Add contributor (#314)Bruce Hoult1-1/+1
2018-12-20ABIs could dedicate other JALR base registersAndrew Waterman1-1/+3
2018-12-20Clean up description of x registers. Add commentary about ABIBruce Hoult1-6/+22
2018-12-19Merge branch 'brucehoult-mips-compact-branches'Andrew Waterman1-2/+2
2018-12-19Update commentary to reflect MIPS r6 conditional branchesBruce Hoult1-2/+2
2018-12-19Improve description of C opcode mapAndrew Waterman1-1/+3
2018-12-19Improve rd'/rs1'/rs2' typesettingAndrew Waterman2-118/+122
2018-12-14Disambiguate P extension in ISA stringsAndrew Waterman1-0/+5
2018-12-14ISA extension dependences can be assumed in ISA name stringsAndrew Waterman2-10/+4
2018-12-14cleanupAndrew Waterman1-2/+2
2018-12-13Make branch immediate description more similar to jumpsAndrew Waterman1-2/+3
2018-12-12Fix some incorrect references to RV32IF (as opposed to RV32IFZicsr)Andrew Waterman2-4/+4
2018-12-11Restate that conditional branches can raise misaligned exceptions in RVIAndrew Waterman1-0/+12
2018-12-10Remark that F depends on ZicsrAndrew Waterman1-6/+7
2018-12-10ISA strings can't leverage extension-dependence propertiesAndrew Waterman1-0/+10
2018-12-10subset -> extensionAndrew Waterman5-21/+21
2018-12-10X*/S*/Z* names must be fully alphabeticalAndrew Waterman1-6/+6
2018-12-10fix typosAndrew Waterman1-2/+2
2018-12-04Debug registers 7A0-7AF are accessible to M-modeAndrew Waterman1-3/+5
2018-12-04Re-version priv specAndrew Waterman1-1/+1
2018-12-04Version of priv spec ready for ratification processAndrew Waterman3-8/+22
2018-12-03Mostly remove RV128 from priv spec, for nowAndrew Waterman3-32/+36
2018-12-03Made clear this document written as if only privileged architecture.Krste Asanovic1-13/+15
2018-12-03Update version numberAndrew Waterman1-1/+1
2018-12-03Adding an marchid for the RVBS open source project (#292)Alexandre Joannou1-1/+2
2018-12-03Remove config string chapter for nowAndrew Waterman2-7/+2
2018-12-03Remove -draft from hypervisor chapter titleAndrew Waterman1-1/+1
2018-12-03Fix Q chapter version numberAndrew Waterman1-1/+1
2018-12-03M-mode editsAndrew Waterman1-27/+22
2018-12-03S-mode editsAndrew Waterman1-5/+5
2018-12-02Remove PLIC chapter from privileged specAndrew Waterman3-3/+2
2018-12-02WIP on M-mode chapterAndrew Waterman3-42/+14
2018-12-02Non-standard -> customAndrew Waterman2-38/+26
2018-12-02Update priv introAndrew Waterman1-20/+16
2018-12-02Revert "Remove date from title page"Andrew Waterman2-2/+4
2018-12-02Update privileged prefaceAndrew Waterman1-2/+23
2018-12-02Clarify misaligned-AMO emulation schemeAndrew Waterman2-12/+18
2018-12-02Use date-based versioning scheme for priv specAndrew Waterman3-16/+9
2018-12-02Remove date from title pageAndrew Waterman1-3/+3
2018-12-02Use American English spelling for consistencyAndrew Waterman2-8/+8
2018-12-01Added clarifying text about raising floating-point exceptions.Krste Asanovic1-1/+6
2018-11-30F depends on ZicsrAndrew Waterman1-1/+2
2018-11-30Hauser commentsAndrew Waterman1-15/+13
2018-11-30Be more tentativeAndrew Waterman1-4/+4
2018-11-3048+-bit instruction-length encoding scheme is not frozenAndrew Waterman1-11/+19
2018-11-30Extend mstatus.TW to U-mode for M/U systems (#286)Andrew Waterman1-6/+14
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