Remove hypervisor draft for release version of specratified-priv-v1.11-sans-hypervisor-draft

5 files changed, 3 insertions, 42 deletions

diff --git a/src/machine.tex b/src/machine.tex
index 3f3d956..e0251c5 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -734,7 +734,7 @@ supported.
 
 \begin{commentary}
 Trapping SRET is necessary to emulate the hypervisor extension
-(see Chapter~\ref{hypervisor}) on implementations that do not provide it.
+on implementations that do not provide it.
 \end{commentary}
 
 \subsubsection{Extension Context Status in {\tt mstatus} Register}
diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex
index 6b66257..c0375a7 100644
--- a/src/priv-csrs.tex
+++ b/src/priv-csrs.tex
@@ -222,41 +222,6 @@ Number    & Privilege & Name & Description \\
 \label{scsrnames}
 \end{table}
 
-\begin{table}[htb!]
-\begin{center}
-\begin{tabular}{|l|l|l|l|}
-\hline
-Number    & Privilege & Name & Description \\
-\hline  
-\multicolumn{4}{|c|}{Hypervisor Trap Setup} \\
-\hline
-\hline
-\tt 0xA00 & HRW  &\tt hstatus    & Hypervisor status register. \\
-\tt 0xA02 & HRW  &\tt hedeleg    & Hypervisor exception delegation register. \\
-\tt 0xA03 & HRW  &\tt hideleg    & Hypervisor interrupt delegation register. \\
-\hline
-\multicolumn{4}{|c|}{Hypervisor Protection and Translation} \\
-\hline
-\tt 0xA80 & HRW  &\tt hgatp      & Hypervisor guest address translation and protection. \\
-\hline
-\multicolumn{4}{|c|}{Hypervisor Background Supervisor Registers} \\
-\hline
-\tt 0x200 & HRW  &\tt bsstatus   & Background supervisor status register. \\
-\tt 0x204 & HRW  &\tt bsie       & Background supervisor interrupt-enable register. \\
-\tt 0x205 & HRW  &\tt bstvec     & Background supervisor trap handler base address. \\
-\tt 0x240 & HRW  &\tt bsscratch  & Background supervisor scratch register. \\
-\tt 0x241 & HRW  &\tt bsepc      & Background supervisor exception program counter. \\
-\tt 0x242 & HRW  &\tt bscause    & Background supervisor trap cause. \\
-\tt 0x243 & HRW  &\tt bstval     & Background supervisor bad address or instruction. \\
-\tt 0x244 & HRW  &\tt bsip       & Background supervisor interrupt pending. \\
-\tt 0x280 & HRW  &\tt bsatp      & Background supervisor address translation and protection. \\
-\hline
-\end{tabular}
-\end{center}
-\caption{Currently allocated RISC-V hypervisor-level CSR addresses.}
-\label{hcsrnames}
-\end{table}
-
 
 \begin{table}[htb!]
 \begin{center}
diff --git a/src/priv-intro.tex b/src/priv-intro.tex
index f909ea6..fb2694a 100644
--- a/src/priv-intro.tex
+++ b/src/priv-intro.tex
@@ -146,9 +146,7 @@ and operating system usage respectively.
 
 Each privilege level has a core set of privileged ISA extensions with optional
 extensions and variants.  For example, machine-mode supports an optional
-standard extension for memory protection.  Also, supervisor mode can be
-extended to support Type-2 hypervisor execution as described in
-Chapter~\ref{hypervisor}.
+standard extension for memory protection.
 
 Implementations might provide anywhere from 1 to 3 privilege modes
 trading off reduced isolation for lower implementation cost, as shown
diff --git a/src/priv-preface.tex b/src/priv-preface.tex
index 80d61b2..20bb2c9 100644
--- a/src/priv-preface.tex
+++ b/src/priv-preface.tex
@@ -16,7 +16,6 @@ modules:
     \hline
     \bf Machine ISA    & \bf 1.11 & \bf Ratified \\
     \bf Supervisor ISA & \bf 1.11 & \bf Ratified \\
-    \em Hypervisor ISA & \em 0.3  & \em Draft \\
     \hline
   \end{tabular}
 \end{table}
diff --git a/src/riscv-privileged.tex b/src/riscv-privileged.tex
index 3bba08a..84d37c6 100644
--- a/src/riscv-privileged.tex
+++ b/src/riscv-privileged.tex
@@ -27,7 +27,7 @@
   $^{1}$SiFive Inc., \\
   $^{2}$CS Division, EECS Department, University of California, Berkeley \\
   {\tt andrew@sifive.com, krste@berkeley.edu} \\
-  \today
+  June 8, 2019
 }
 
 \date{} 
@@ -76,7 +76,6 @@ Andrew Waterman and Krste Asanovi\'{c}, RISC-V Foundation, \privmonthyear.
 \input{priv-csrs}
 \input{machine}
 \input{supervisor}
-\input{hypervisor}
 \input{priv-insns}
 
 \input{priv-history}