diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/hypervisor.tex | 47 | ||||
| -rw-r--r-- | src/priv-csrs.tex | 5 |
2 files changed, 52 insertions, 0 deletions
diff --git a/src/hypervisor.tex b/src/hypervisor.tex index 6ac03a1..47b90b2 100644 --- a/src/hypervisor.tex +++ b/src/hypervisor.tex @@ -404,6 +404,53 @@ indicating reads to the corresponding counter will cause an exception when V=1. Hence, they are effectively \warl\ fields. +\subsection{Hypervisor Time Delta Registers ({\tt htimedelta}, {\tt htimedeltah})} + +The {\tt htimedelta} CSR is a read/write register that contains the delta +between the value of the {\tt time} CSR and the value returned in VS-mode or +VU-mode. +That is, reading the {\tt time} CSR in VS or VU mode returns the sum of the +contents of {\tt htimedelta} and the actual value of {\tt time}. + +\begin{figure*}[h!] +{\footnotesize +\begin{center} +\begin{tabular}{@{}J} +\instbitrange{63}{0} \\ +\hline +\multicolumn{1}{|c|}{\tt htimedelta} \\ +\hline +64 \\ +\end{tabular} +\end{center} +} +\vspace{-0.1in} +\caption{Hypervisor time delta register, HSXLEN=64.} +\label{hdeltareg} +\end{figure*} + +For HSXLEN=32 only, {\tt htimedelta} holds the lower 32 bits of the +delta, and {\tt htimedeltah} holds the upper 32 bits of the delta. + +\begin{figure*}[h!] +{\footnotesize +\begin{center} +\begin{tabular}{@{}J} +\instbitrange{31}{0} \\ +\hline +\multicolumn{1}{|c|}{\tt htimedelta} \\ +\hline +\multicolumn{1}{|c|}{\tt htimedeltah} \\ +\hline +32 \\ +\end{tabular} +\end{center} +} +\vspace{-0.1in} +\caption{Hypervisor time delta registers, HSXLEN=32.} +\label{hdeltahreg} +\end{figure*} + \subsection{Hypervisor Guest Address Translation and Protection Register ({\tt hgatp})} \label{sec:hgatp} diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex index fe78bab..0b4244f 100644 --- a/src/priv-csrs.tex +++ b/src/priv-csrs.tex @@ -241,6 +241,11 @@ Number & Privilege & Name & Description \\ \hline \tt 0x680 & HRW &\tt hgatp & Hypervisor guest address translation and protection. \\ \hline +\multicolumn{4}{|c|}{Hypervisor Counter/Timer Virtualization Registers} \\ +\hline +\tt 0xA01 & HRW &\tt htimedelta & Delta for VS/VU-mode timer. \\ +\tt 0xA81 & HRW &\tt htimedeltah & Upper 32 bits of {\tt htimedelta}, RV32I only. \\ +\hline \multicolumn{4}{|c|}{Virtual Supervisor Registers} \\ \hline \tt 0x200 & HRW &\tt vsstatus & Virtual supervisor status register. \\ |