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Diffstat (limited to 'src/zicsr.adoc')
| -rw-r--r-- | src/zicsr.adoc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/zicsr.adoc b/src/zicsr.adoc index 3c4eed4..aabe032 100644 --- a/src/zicsr.adoc +++ b/src/zicsr.adoc @@ -85,11 +85,10 @@ effects regardless of _rd_ and _rs1_ fields. (((CSR, side effects))) [[csrsideeffects]] -.Conditions determining whether a CSR instruction reads or writes the -specified CSR. +.Conditions determining whether a CSR instruction reads or writes the specified CSR. [cols="<,^,^,^,^",options="header",] |=== -|Register operand | | | | +|_Register operand_| | | | |Instruction |_rd_ is `x0` |_rs1_ is `x0` |Reads CSR |Writes CSR |CSRRW |Yes |– |No |Yes @@ -100,7 +99,7 @@ specified CSR. |CSRRS/CSRRC |– |No |Yes |Yes -|Immediate operand | | | | +|_Immediate operand_| | | | |Instruction |_rd_ is `x0` |_uimm_ latexmath:[$=$]0 |Reads CSR |Writes CSR @@ -172,7 +171,6 @@ in the CSR when the old value is not required: CSRS/CSRC _csr, rs1_; CSRSI/CSRCI _csr, uimm_. ==== CSR Access Ordering -(((CSR, access ordering))) Each RISC-V hart normally observes its own CSR accesses, including its implicit CSR accesses, as performed in program order. In particular, @@ -184,6 +182,8 @@ modified by the CSR state. Furthermore, an explicit CSR read returns the CSR state before the execution of the instruction, while an explict CSR write suppresses and overrides any implicit writes or modifications to the same CSR by the same instruction. +(((CSR, access ordering))) +(((CSR, access effects))) Likewise, any side effects from an explicit CSR access are normally observed to occur synchronously in program order. Unless specified |