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Diffstat (limited to 'src/zicsr.adoc')
| -rw-r--r-- | src/zicsr.adoc | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/zicsr.adoc b/src/zicsr.adoc index ad8a916..2a1ddbd 100644 --- a/src/zicsr.adoc +++ b/src/zicsr.adoc @@ -1,5 +1,5 @@ [[csrinsts]] -== Zicsr, Control and Status Register (CSR) Instructions, Version 2.0 +== "Zicsr" Control and Status Register (CSR) Instructions, Version 2.0 RISC-V defines a separate address space of 4096 Control and Status registers associated with each hart. This chapter defines the full set @@ -18,7 +18,6 @@ chapter. ==== === CSR Instructions -((CSR)) All CSR instructions atomically read-modify-write a single CSR, whose CSR specifier is encoded in the 12-bit _csr_ field of the instruction @@ -89,6 +88,7 @@ effects regardless of _rd_ and _rs1_ fields. [cols="<,^,^,^,^",options="header",] |=== |_Register operand_| | | | + |Instruction |_rd_ is `x0` |_rs1_ is `x0` |Reads CSR |Writes CSR |CSRRW |Yes |– |No |Yes @@ -101,8 +101,7 @@ effects regardless of _rd_ and _rs1_ fields. |_Immediate operand_| | | | -|Instruction |_rd_ is `x0` |_uimm_ latexmath:[$=$]0 |Reads CSR |Writes -CSR +|Instruction |_rd_ is `x0` |_uimm_ latexmath:[$=$]0 |Reads CSR |Writes CSR |CSRRWI |Yes |– |No |Yes @@ -223,7 +222,7 @@ such CSRs (e.g., taking an interrupt because of a change in `mip`) are also ordered as device input. ==== -Most CSRs (including, e.g., the `fcsr`) are not visible to other harts; +Most CSRs (including, e.g., the "fcsr") are not visible to other harts; their accesses can be freely reordered in the global memory order with respect to FENCE instructions without violating this specification. |