diff options
Diffstat (limited to 'src/supervisor.tex')
| -rw-r--r-- | src/supervisor.tex | 22 |
1 files changed, 7 insertions, 15 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index 0464a8e..45c1c38 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -1438,13 +1438,6 @@ follows: \begin{enumerate} -\item If XLEN equals VALEN, proceed. - (For Sv32, VALEN=32.) - Otherwise, check whether each bit of $va$[XLEN-1:VALEN] is equal to - $va$[VALEN-1]. - If not, stop and raise a page-fault exception corresponding to the - original access type. - \item Let $a$ be ${\tt satp}.ppn \times \textrm{PAGESIZE}$, and let $i=\textrm{LEVELS} - 1$. (For Sv32, PAGESIZE=$2^{12}$ and LEVELS=2.) \item Let $pte$ be the value of the PTE at address @@ -1456,11 +1449,11 @@ follows: page-fault exception corresponding to the original access type. \item Otherwise, the PTE is valid. - If $pte.r=1$ or $pte.x=1$, go to step 6. + If $pte.r=1$ or $pte.x=1$, go to step 5. Otherwise, this PTE is a pointer to the next level of the page table. Let $i=i-1$. If $i<0$, stop and raise a page-fault exception corresponding to the original access type. Otherwise, let - $a=pte.ppn \times \textrm{PAGESIZE}$ and go to step 3. + $a=pte.ppn \times \textrm{PAGESIZE}$ and go to step 2. \item A leaf PTE has been found. Determine if the requested memory access is allowed by the $pte.r$, $pte.w$, $pte.x$, and $pte.u$ bits, given the @@ -1478,7 +1471,7 @@ follows: $pte.d$ to 1. \item If this access violates a PMA or PMP check, raise an access-fault exception corresponding to the original access type. - \item This update and the loading of $pte$ in step 3 must be atomic; in + \item This update and the loading of $pte$ in step 2 must be atomic; in particular, no intervening store to the PTE may be perceived to have occurred in-between. \end{itemize} @@ -1647,8 +1640,7 @@ A page-fault exception is raised if the physical address is insufficiently aligned. The algorithm for virtual-to-physical address translation is the same as in -Section~\ref{sv32algorithm}, except VALEN equals 39, LEVELS equals 3, and -PTESIZE equals 8. +Section~\ref{sv32algorithm}, except LEVELS equals 3 and PTESIZE equals 8. \section{Sv48: Page-Based 48-bit Virtual-Memory System} \label{sec:sv48} @@ -1781,6 +1773,6 @@ physically aligned to a boundary equal to its size. A page-fault exception is raised if the physical address is insufficiently aligned. -The algorithm for virtual-to-physical address translation is the same as in -Section~\ref{sv32algorithm}, except VALEN equals 48, LEVELS equals 4, and -PTESIZE equals 8. +The algorithm for virtual-to-physical address translation is the same +as in Section~\ref{sv32algorithm}, except LEVELS equals 4 and PTESIZE +equals 8. |