diff options
Diffstat (limited to 'src/sstc.adoc')
| -rw-r--r-- | src/sstc.adoc | 34 |
1 files changed, 19 insertions, 15 deletions
diff --git a/src/sstc.adoc b/src/sstc.adoc index 8198349..49be41a 100644 --- a/src/sstc.adoc +++ b/src/sstc.adoc @@ -38,13 +38,15 @@ bits, while accesses to the `stimecmph` CSR access the high 32 bits of `stimecmp The CSR numbers for `stimecmp` / `stimecmph` are 0x14D / 0x15D (within the Supervisor Trap Setup block of CSRs). -A supervisor timer interrupt becomes pending - as reflected in the STIP bit in -the mip and sip registers - whenever time contains a value greater than or -equal to stimecmp, treating the values as unsigned integers. Writes to stimecmp -are guaranteed to be reflected in STIP eventually, but not necessarily -immediately. The interrupt remains posted until stimecmp becomes greater than -time - typically as a result of writing stimecmp. The interrupt will be taken -based on the standard interrupt enable and delegation rules. +A supervisor timer interrupt becomes pending, as reflected in the STIP bit in +the `mip` and `sip` registers whenever `time` contains a value greater than or +equal to `stimecmp`, treating the values as unsigned integers. +If the result of this comparison changes, it is guaranteed to be reflected in +STIP eventually, but not necessarily immediately. +The interrupt remains posted until `stimecmp` becomes greater than `time`, +typically as a result of writing `stimecmp`. +The interrupt will be taken based on the standard interrupt enable and +delegation rules. [NOTE] ==== @@ -122,14 +124,16 @@ The proposed CSR numbers for `vstimecmp` / `vstimecmph` are 0x24D / 0x25D (withi the Virtual Supervisor Registers block of CSRs, and mirroring the CSR numbers for stimecmp/stimecmph). -A virtual supervisor timer interrupt becomes pending - as reflected in the -VSTIP bit in the `hip` register - whenever (`time` + `htimedelta`), truncated to 64 -bits, contains a value greater than or equal to `vstimecmp`, treating the values -as unsigned integers. Writes to `vstimecmp` and `htimedelta` are guaranteed to be -reflected in VSTIP eventually, but not necessarily immediately. The interrupt -remains posted until `vstimecmp` becomes greater than (`time` + `htimedelta`) - -typically as a result of writing `vstimecmp`. The interrupt will be taken based -on the standard interrupt enable and delegation rules while V=1. +A virtual supervisor timer interrupt becomes pending, as reflected in the +VSTIP bit in the `hip` register, whenever (`time` + `htimedelta`), truncated +to 64 bits, contains a value greater than or equal to `vstimecmp`, treating +the values as unsigned integers. +If the result of this comparison changes, it is guaranteed to be reflected in +VSTIP eventually, but not necessarily immediately. +The interrupt remains posted until `vstimecmp` becomes greater than (`time` ++ `htimedelta`), typically as a result of writing `vstimecmp`. +The interrupt will be taken based on the standard interrupt enable and +delegation rules while V=1. [NOTE] ==== |