diff options
Diffstat (limited to 'src/smstateen.adoc')
| -rw-r--r-- | src/smstateen.adoc | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/smstateen.adoc b/src/smstateen.adoc index 6e18156..beebc4f 100644 --- a/src/smstateen.adoc +++ b/src/smstateen.adoc @@ -247,7 +247,8 @@ The JVT bit controls access to the JVT CSR provided by the Zcmt extension. {bits: 1, name: 'C'}, {bits: 1, name: 'FCSR'}, {bits: 1, name: 'JVT'}, -{bits: 53, name: 'WPRI'}, +{bits: 52, name: 'WPRI'}, +{bits: 1, name: 'P1P14'}, {bits: 1, name: 'P1P13'}, {bits: 1, name: 'CONTEXT'}, {bits: 1, name: 'IMSIC'}, @@ -285,6 +286,9 @@ hcontext CSRs provided by the Sdtrig ISA extension. The P1P13 bit in mstateen0 controls access to the hedelegh introduced by Privileged Specification Version 1.13. +The P1P14 bit in mstateen0 controls access to the srmcfg CSR introduced by +Privileged Specification Version 1.14. + === Hypervisor State Enable Register (hstateen0) [wavedrom, ,svg] @@ -405,4 +409,4 @@ it is unclear whether they will ever be needed, and it is believed the rate of consumption of bits in the first group, registers numbered 0-3, will be slow enough that any looming shortage will be perceptible many years in advance. At the moment, it is not known even how many years it may take to exhaust just -`mstateen0`, `sstateen0`, and `hstateen0`.
\ No newline at end of file +`mstateen0`, `sstateen0`, and `hstateen0`. |