diff options
Diffstat (limited to 'src/smcntrpmf.adoc')
| -rw-r--r-- | src/smcntrpmf.adoc | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/src/smcntrpmf.adoc b/src/smcntrpmf.adoc index 94e6314..4838f2d 100644 --- a/src/smcntrpmf.adoc +++ b/src/smcntrpmf.adoc @@ -1,7 +1,6 @@ [[smcntrpmf]] == "Smcntrpmf" Cycle and Instret Privilege Mode Filtering, Version 1.0 -[[intro]] === Introduction The cycle and instret counters serve to support user mode self-profiling usages, wherein a user can read the counter(s) twice and compute the delta(s) to evaluate user software performance and behavior. By default, these counters are not filtered by privilege mode, and thus they continue to increment while traps (e.g., page faults or interrupts) to more privileged code are handled. This causes two problems: @@ -11,7 +10,6 @@ The cycle and instret counters serve to support user mode self-profiling usages, Smcntrpmf remedies these issues by introducing privilege mode filtering for the cycle and instret counters. -[[csrs]] === CSRs ==== Machine Counter Configuration (`mcyclecfg`, `minstretcfg`) Registers @@ -21,7 +19,7 @@ mcyclecfg and minstretcfg are 64-bit registers that configure privilege mode fil [cols="^1,^1,^1,^1,^1,^1,^5",stripes=even,options="header"] |==== |63 |62 |61 |60 |59 |58 |57:0 -|0 |MINH |SINH |UINH |VSINH |VUINH |_WPRI_ +|0 |MINH |SINH |UINH |VSINH |VUINH |_WPRI_ |==== [cols="15%,85%",options="header"] @@ -36,7 +34,7 @@ mcyclecfg and minstretcfg are 64-bit registers that configure privilege mode fil When all __x__INH bits are zero, event counting is enabled in all modes. -For each bit in 61:58, if the associated privilege mode is not implemented, the bit is read-only zero. Bits 57:56 are reserved for possible future modes. +For each bit in 61:58, if the associated privilege mode is not implemented, the bit is read-only zero. For RV32, bits 63:32 of mcyclecfg can be accessed via the mcyclecfgh CSR, and bits 63:32 of minstretcfg can be accessed via the minstretcfgh CSR. @@ -51,7 +49,6 @@ The more natural CSR number for mcyclecfg would be 0x320, but that was allocated This register format matches that specified for programmable counters by Sscofpmf. The bit position for the OF bit (bit 63) is read-only 0, since these counters do not generate local counter overflow interrupts on overflow. ==== -[[behavior]] === Counter Behavior The fundamental behavior of cycle and instret is modified in that counting does not occur while executing in an inhibited privilege mode. Further, the following defines how transitions between a non-inhibited privilege mode and an inhibited privilege mode are counted. |