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-rw-r--r--src/rv32.tex4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/rv32.tex b/src/rv32.tex
index 8b386c1..0ab911c 100644
--- a/src/rv32.tex
+++ b/src/rv32.tex
@@ -413,7 +413,7 @@ register-register instructions. No integer computational instructions
cause arithmetic exceptions.
\begin{commentary}
-We did not include special instruction set support for overflow checks
+We did not include special instruction-set support for overflow checks
on integer arithmetic operations in the base instruction set, as many
overflow checks can be cheaply implemented using RISC-V branches.
Overflow checking for unsigned addition requires only a single
@@ -754,7 +754,7 @@ boundary.
\begin{commentary}
Instruction fetch misaligned exceptions are not possible on machines
that support extensions with 16-bit aligned instructions, such as the
-compressed instruction set extension, C.
+compressed instruction-set extension, C.
\end{commentary}
Return-address prediction stacks are a common feature of