diff options
Diffstat (limited to 'src/rv32.adoc')
| -rw-r--r-- | src/rv32.adoc | 52 |
1 files changed, 47 insertions, 5 deletions
diff --git a/src/rv32.adoc b/src/rv32.adoc index 858230b..23371ac 100644 --- a/src/rv32.adoc +++ b/src/rv32.adoc @@ -29,13 +29,16 @@ instructions as a single trap. ==== The standard RISC-V assembly language syntax is documented in the Assembly Programmer’s Manual cite:[riscv-asm-manual]. +==== +[NOTE] +==== Most of the commentary for RV32I also applies to the RV64I base. ==== === Programmers’ Model for Base Integer ISA -<<img-gprs>> shows the unprivileged state for the base +<<gprs>> shows the unprivileged state for the base integer ISA. For RV32I, the 32 `x` registers are each 32 bits wide, i.e., XLEN=32. Register `x0` is hardwired with all bits equal to 0. General purpose registers `x1`–`x31` hold values that various @@ -45,9 +48,48 @@ complement signed binary integers or unsigned binary integers. There is one additional unprivileged register: the program counter `pc` holds the address of the current instruction. -[[img-gprs]] +[[gprs]] .RISC-V base unprivileged integer register state. -image::base-unpriv-reg-state.png[base,180,1000,align="center"] +[col[s="<|^|>"|option[s="header",width="50%",align="center"grid="none"] +|=== +<| [.small]#XLEN-1#| >| [.small]#0# +3+^| [.small]#x0/zero# +3+^| [.small]#x1# +3+^| [.small]#x2# +3+^| [.small]#x3# +3+^| [.small]#x4# +3+^| [.small]#x5# +3+^| [.small]#x6# +3+^| [.small]#x7# +3+^| [.small]#x8# +3+^| [.small]#x9# +3+^| [.small]#x10# +3+^| [.small]#x11# +3+^| [.small]#x12# +3+^| [.small]#x13# +3+^| [.small]#x14# +3+^| [.small]#x15# +3+^| [.small]#x16# +3+^| [.small]#x17# +3+^| [.small]#x18# +3+^| [.small]#x19# +3+^| [.small]#x20# +3+^| [.small]#x21# +3+^| [.small]#x22# +3+^| [.small]#x23# +3+^| [.small]#x24# +3+^| [.small]#x25# +3+^| [.small]#x26# +3+^| [.small]#x27# +3+^| [.small]#x28# +3+^| [.small]#x29# +3+^| [.small]#x30# +3+^| [.small]#x31# +3+^| [.small]#XLEN# +| [.small]#31#| >| [.small]#0# +3+^| [.small]#pc# +3+^| [.small]#XLEN# +|=== There is no dedicated stack pointer or subroutine return address link register in the Base Integer ISA; the instruction encoding allows any @@ -972,7 +1014,7 @@ simulation/emulation. |=== |Instruction |Constraints |Code Points |Purpose -|LUI |_rd_=`x0` |latexmath:[$2^{20}$] .18+<.>m|_Reserved for future standard use_ +|LUI |_rd_=`x0` |latexmath:[$2^{20}$] .18+<.^m|_Reserved for future standard use_ |AUIPC |_rd_=`x0` |latexmath:[$2^{20}$] @@ -1010,7 +1052,7 @@ simulation/emulation. |FENCE |_rd_=_rs1_=`x0`, _fm_=0, _pred_=W, _succ_=0 |1 |PAUSE -|SLTI |_rd_=`x0` |latexmath:[$2^{17}$] .7+<.>m|_Designated for custom use_ +|SLTI |_rd_=`x0` |latexmath:[$2^{17}$] .7+<.^m|_Designated for custom use_ |SLTIU|_rd_=`x0` |latexmath:[$2^{17}$] |