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Diffstat (limited to 'src/rv32.adoc')
-rw-r--r-- | src/rv32.adoc | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/src/rv32.adoc b/src/rv32.adoc index 8fccaba..ba02728 100644 --- a/src/rv32.adoc +++ b/src/rv32.adoc @@ -177,7 +177,6 @@ bit 31 of the instruction to speed sign-extension circuitry. include::images/wavedrom/instruction_formats.adoc[] [[base_instr]] .RISC-V base instruction formats -image::image_placeholder.png[] Each immediate subfield in <<base_instr>> above is labeled with the bit position (imm[x]) in the immediate value being produced, rather than the bit position within the instruction’s immediate field as is usually done. @@ -207,7 +206,6 @@ on the handling of immediates, as shown in <<baseinstformatsimm>>. include::images/wavedrom/immediate_variants.adoc[] [[baseinstformatsimm]] .RISC-V base instruction formats. -image::image_placeholder.png[] The only difference between the S and B formats is that the 12-bit immediate field is used to encode branch offsets in multiples of 2 in @@ -229,7 +227,6 @@ instruction bit (inst[_y_]) produces each bit of the immediate value. include::images/wavedrom/immediate.adoc[] [[immtypes]] .Immediate variants for I, S, B, U, and J -image::image_placeholder.png[] [NOTE] ==== @@ -296,7 +293,6 @@ comparing the results of ADD and ADDW on the operands. include::images/wavedrom/integer_computational.adoc[] .Integer Computational Instructions -image::image_placeholder.png[] ADDI adds the sign-extended 12-bit immediate to register _rs1_. Arithmetic overflow is ignored and the result is simply the low XLEN @@ -319,7 +315,6 @@ inversion of register _rs1_ (assembler pseudoinstruction NOT _rd, rs_). include::images/wavedrom/int-comp-slli-srli-srai.adoc[] [[int-comp-slli-srli-srai]] .Integer register-immediate, SLLI, SRLI, SRAI -image::image_placeholder.png[] Shifts by a constant are encoded as a specialization of the I-type format. The operand to be shifted is in _rs1_, and the shift amount is @@ -332,7 +327,6 @@ original sign bit is copied into the vacated upper bits). include::images/wavedrom/int-comp-lui-aiupc.adoc[] [[int-comp-lui-aiupc]] .Integer register-immediate, U-immediate -image::image_placeholder.png[] LUI (load upper immediate) is used to build 32-bit constants and uses the U-type format. LUI places the 32-bit U-immediate value into the @@ -373,7 +367,6 @@ operation. include::images/wavedrom/int_reg-reg.adoc[] [[int-reg-reg]] .Integer register-register -image::image_placeholder.png[] ADD performs the addition of _rs1_ and _rs2_. SUB performs the subtraction of _rs2_ from _rs1_. Overflows are ignored and the low XLEN @@ -393,7 +386,6 @@ the lower 5 bits of register _rs2_. include::images/wavedrom/nop.adoc[] [[nop]] .NOP instructions -image::image_placeholder.png[] The NOP instruction does not change any architecturally visible state, except for advancing the `pc` and incrementing any applicable @@ -458,7 +450,6 @@ a JAL with _rd_=`x0`. include::images/wavedrom/ct-unconditional.adoc[] [[ct-unconditional]] .The unconditional-jump instruction, JAL -image::image_placeholder.png[] The indirect jump instruction JALR (jump and link register) uses the I-type encoding. The target address is obtained by adding the @@ -471,7 +462,6 @@ required. include::images/wavedrom/ct-unconditional-2.adoc[] [[ct-unconditional-2]] .The indirect unconditional-jump instruction, JALR -image::image_placeholder.png[] [NOTE] ==== @@ -567,7 +557,6 @@ give the target address. The conditional branch range is include::images/wavedrom/ct-conditional.adoc[] [[ct-conditional]] .Conditional branches -image::image_placeholder.png[] Branch instructions compare two registers. BEQ and BNE take the branch if registers _rs1_ and _rs2_ are equal or unequal respectively. BLT and @@ -702,7 +691,6 @@ memory byte addresses to the less-significant register bytes. include::images/wavedrom/load_store.adoc[] [[load-store,load and store]] .Load and store instructions -image::image_placeholder.png[] Load and store instructions transfer a value between the registers and memory. Loads are encoded in the I-type format and stores are S-type. @@ -792,7 +780,6 @@ are aligned. include::images/wavedrom/mem_order.adoc[] [[mem-order]] .Memory ordering instructions -image::image_placeholder.png[] The FENCE instruction is used to order device I/O and memory accesses as viewed by other RISC-V harts and external devices or coprocessors. Any @@ -901,7 +888,6 @@ hardware. include::images/wavedrom/env_call-breakpoint.adoc[] [[env-call]] .Evironment call and breakpoint instructions -image::image_placeholder.png[] These two instructions cause a precise requested trap to the supporting execution environment. |