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-\chapter{Preface}
-
-This is {\bf a draft of} version 1.11 of the RISC-V privileged
-architecture proposal.  Changes from version 1.10 include:
-
-\begin{itemize}
-  \parskip 0pt
-  \itemsep 1pt
-\item Improvements to the description and commentary.
-\item Added a draft proposal for a hypervisor extension.
-\item Specified which interrupt sources are reserved for standard use.
-\item Added specification that xRET instructions may, but are not
-  required to, clear LR reservations if A extension present.
-\item The virtual-memory system no longer permits supervisor mode to execute
-  instructions from user pages, regardless of the SUM setting.
-\item Made the {\tt mstatus}.MPP field \warl, rather than \wlrl.
-\item Made the unused {\em x}{\tt ip} fields \wpri, rather than \wiri.
-\item Made the unused {\tt misa} fields \wlrl, rather than \wiri.
-\item Made the unused {\tt pmpaddr} and {\tt pmpcfg} fields \warl, rather than \wiri.
-\item Required all harts in a system to employ the same PTE-update scheme as each other.
-\item Rectified an editing error that misdescribed the mechanism by which
-  {\tt mstatus}.{\em x}IE is written upon an exception.
-\item Added the constraint that if a PMA supports LR, SC, or AMOs, but traps
-  misaligned LR, SC, or AMOs, then it also must trap
-  misaligned loads and stores.
-\item Specified the behavior of the {\tt misa} and {\em x}{\tt epc} registers in
-  systems with variable IALIGN.
-\item Specified the behavior of writing self-contradictory values to the
-  {\tt misa} register.
-\item Specified semantics for PMP regions coarser than four bytes.
-\item Specified contents of CSRs across XLEN modification.
-\end{itemize}
-
-\newpage
-
-\section*{Preface to Version 1.10}
-
-This is version 1.10 of the RISC-V privileged
-architecture proposal.  Changes from version 1.9.1 include:
-
-\begin{itemize}
-  \parskip 0pt
-  \itemsep 1pt
-\item The previous version of this document was released under a
-  Creative Commons Attribution 4.0 International License by the
-  original authors, and this and future versions of this document will
-  be released under the same license.
-\item The explicit convention on shadow CSR addresses has been removed
-  to reclaim CSR space.  Shadow CSRs can still be added as needed.
-\item The {\tt mvendorid} register now contains the JEDEC code of the
-  core provider as opposed to a code supplied by the Foundation.  This
-  avoids redundancy and offloads work from the Foundation.
-\item The interrupt-enable stack discipline has been simplified.
-\item An optional mechanism to change the base ISA used by supervisor
-  and user modes has been added to the {\tt mstatus} CSR, and the
-  field previously called Base in {\tt misa} has been renamed to {\tt
-    MXL} for consistency.
-\item Clarified expected use of XS to summarize additional extension
-  state status fields in {\tt mstatus}.
-\item Optional vectored interrupt support has been added to the
-  {\tt mtvec} and {\tt stvec} CSRs.
-\item The SEIP and UEIP bits in the {\tt mip} CSR have been redefined
-  to support software injection of external interrupts.
-  \item The {\tt mbadaddr} register has been subsumed by a more
-    general {\tt mtval} register that can now capture bad
-    instruction bits on an illegal instruction fault to speed
-    instruction emulation.
-\item The machine-mode base-and-bounds translation and protection
-  schemes have been removed from the specification as part of moving
-  the virtual memory configuration to {\tt sptbr} (now {\tt satp}).  Some of the
-  motivation for the base and bound schemes are now covered by the PMP
-  registers, but space remains available in {\tt mstatus} to add these
-  back at a later date if deemed useful.
-\item In systems with only M-mode, or with both M-mode and U-mode but
-  without U-mode trap support, the {\tt medeleg} and {\tt mideleg}
-    registers now do not exist, whereas previously they returned zero.
-\item Virtual-memory page faults now have {\tt mcause} values distinct from
-  physical-memory access exceptions.  Page-fault exceptions can now be
-  delegated to S-mode without delegating exceptions generated by PMA
-  and PMP checks.
-\item An optional physical-memory protection (PMP) scheme has been proposed.
-\item The supervisor virtual memory configuration has been moved from the
-  {\tt mstatus} register to the {\tt sptbr} register.  Accordingly, the
-  {\tt sptbr} register has been renamed to {\tt satp} (Supervisor Address
-  Translation and Protection) to reflect its broadened role.
-\item The SFENCE.VM instruction has been removed in favor of the improved
-  SFENCE.VMA instruction.
-\item The {\tt mstatus} bit MXR has been exposed to S-mode via {\tt sstatus}.
-\item The polarity of the PUM bit in {\tt sstatus} has been inverted to
-  shorten code sequences involving MXR.  The bit has been renamed to SUM.
-\item Hardware management of page-table entry Accessed and Dirty bits has
-  been made optional; simpler implementations may trap to software to
-  set them.
-\item The counter-enable scheme has changed, so that S-mode can
-  control availability of counters to U-mode.
-\item H-mode has been removed, as we are focusing on recursive
-  virtualization support in S-mode.  The encoding space has been
-  reserved and may be repurposed at a later date.
-\item A mechanism to improve virtualization performance by
-  trapping S-mode virtual-memory management operations has been added.
-\item The Supervisor Binary Interface (SBI) chapter has been removed, so
-  that it can be maintained as a separate specification.
-\end{itemize}
-
-\newpage
-
-\section*{Preface to Version 1.9.1}
-
-This is version 1.9.1 of the RISC-V privileged architecture
-proposal.  Changes from version 1.9 include:
-
-\begin{itemize}
-  \parskip 0pt
-  \itemsep 1pt
-\item Numerous additions and improvements to the commentary sections.
-\item Change configuration string proposal to be use a search process
-  that supports various formats including Device Tree String and
-  flattened Device Tree.
-\item Made {\tt misa} optionally writable to support modifying base
-  and supported ISA extensions.  CSR address of {\tt misa} changed.
-\item Added description of debug mode and debug CSRs.
-\item Added a hardware performance monitoring scheme.  Simplified the
-  handling of existing hardware counters, removing privileged versions
-  of the counters and the corresponding delta registers.
-\item Fixed description of SPIE in presence of user-level interrupts.
-\end{itemize}