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diff --git a/src/priv-preface.adoc b/src/priv-preface.adoc
index ba36ebb..936409c 100644
--- a/src/priv-preface.adoc
+++ b/src/priv-preface.adoc
@@ -1,10 +1,10 @@
[colophon]
= Preface
-[.big]*_Preface to Version 20240326_*
+[.big]*_Preface to Version 20240528_*
This document describes the RISC-V privileged architecture. This
-release, version 20240213, contains the following versions of the RISC-V ISA
+release, version 20240528, contains the following versions of the RISC-V ISA
modules:
[%autowidth,float="center",align="center",cols="^,<,^",options="header",]
@@ -25,24 +25,26 @@ _Supervisor ISA_ +
*Svadu Extension* +
*Sstc* +
*Sscofpmf* +
-*Hypervisor ISA*
+*Hypervisor ISA* +
+_Shlcofideleg_
|_1.13_ +
-*1.0.0* +
-*1.0.0* +
-*1.0.0* +
-*1.0.0* +
-*1.0.0* +
+*1.0* +
+*1.0* +
+*1.0* +
+*1.0* +
+*1.0* +
+*1.0* +
_1.13_ +
-*1.0.0* +
-_0.1_ +
*1.0* +
*1.0* +
*1.0* +
*1.0* +
*1.0* +
*1.0* +
-*1.0*
+*1.0* +
+*1.0* +
+_0.1_
|_Draft_ +
*Ratified* +
@@ -50,7 +52,6 @@ _0.1_ +
*Ratified* +
*Ratified* +
*Ratified* +
-_Draft_ +
*Ratified* +
_Draft_ +
*Ratified* +
@@ -59,63 +60,21 @@ _Draft_ +
*Ratified* +
*Ratified* +
*Ratified* +
-*Ratified*
-|===
-
-The changes in this version of the document include:
-
-* The inclusion of all ratified extensions through March 2024.
-* The concept of vacant memory regions has been superseded by inaccessible memory or I/O regions.
-
-[.big]*_Preface to Version 20240213_*
-
-This document describes the RISC-V privileged architecture. This
-release, version 20240213, contains the following versions of the RISC-V ISA
-modules:
-
-[%autowidth,float="center",align="center",cols="^,<,^",options="header",]
-|===
-|Module |Version |Status
-|_Machine ISA_ +
-_Supervisor ISA_ +
-_Smrnmi Extension_ +
-*Svade Extension* +
-*Svnapot Extension* +
-*Svpbmt Extension* +
-*Svinval Extension* +
-*Svadu Extension* +
-*Hypervisor ISA*
-|_1.13_ +
-_1.13_ +
-_0.1_ +
-*1.0* +
-*1.0* +
-*1.0* +
-*1.0* +
-*1.0* +
-*1.0*
-|_Draft_ +
-_Draft_ +
-_Draft_ +
-*Ratified* +
-*Ratified* +
-*Ratified* +
*Ratified* +
*Ratified* +
-*Ratified*
+_Draft_
|===
-The following changes have been made since version 1.12, which, while
-not strictly backwards compatible, are not anticipated to cause software
-portability problems in practice:
+The following changes have been made since version 1.12 of the Machine and
+Supervisor ISAs, which, while not strictly backwards compatible, are not
+anticipated to cause software portability problems in practice:
* Redefined `misa`.MXL to be read-only, making MXLEN a constant.
* Added the constraint that SXLEN&#8805;UXLEN.
-Additionally, the following compatible changes have been made to the Machine ISA since
-version 1.12:
+Additionally, the following compatible changes have been
+made to the Machine and Supervisor ISAs since version 1.12:
-* Transliterated the document from LaTeX into AsciiDoc.
* Defined the `misa`.V field to reflect that the V extension has been
implemented.
* Defined the RV32-only `medelegh` and `hedelegh` CSRs.
@@ -125,7 +84,13 @@ implemented.
* Defined hardware error and software check exception codes.
* Specified synchronization requirements when changing the PBMTE fields
in `menvcfg` and `henvcfg`.
-* Incorporated Svade and Svadu extension specifications.
+* Exposed count-overflow interrups to VS-mode via the Shlcofideleg extension.
+
+Finally, the following clarifications and document improvments have been made
+since the last document release:
+
+* Transliterated the document from LaTeX into AsciiDoc.
+* Included all ratified extensions through March 2024.
* Clarified that "platform- or custom-use" interrupts are actually
"platform-use interrupts", where the platform can choose to make some custom.
* Clarified semantics of explicit accesses to CSRs wider than XLEN bits.
@@ -138,7 +103,7 @@ in `menvcfg` and `henvcfg`.
be set to a nonzero value but sometimes not.
* Clarified exception behavior of unimplemented or inaccessible CSRs.
* Clarified that Svpbmt allows implementations to override additional PMAs.
-* Exposed count-overflow interrups to VS-mode.
+* Replaced the concept of vacant memory regions with inaccessible memory or I/O regions.
[.big]*_Preface to Version 20211203_*