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Diffstat (limited to 'src/priv-csrs.tex')
| -rw-r--r-- | src/priv-csrs.tex | 62 |
1 files changed, 33 insertions, 29 deletions
diff --git a/src/priv-csrs.tex b/src/priv-csrs.tex index c1bd6d8..5510452 100644 --- a/src/priv-csrs.tex +++ b/src/priv-csrs.tex @@ -10,10 +10,10 @@ The privileged architecture requires the Zicsr extension; which other privileged instructions are required depends on the privileged-architecture feature set. -In addition to the user-level +In addition to the unprivileged state described in Volume I of this manual, an implementation may contain additional CSRs, accessible by some subset of the privilege -levels using the CSR instructions described in the user-level manual. +levels using the CSR instructions described in Volume~I. In this chapter, we map out the CSR address space. The following chapters describe the function of each of the CSRs according to privilege level, as well as the other privileged instructions which @@ -22,6 +22,9 @@ Note that although CSRs and instructions are associated with one privilege level, they are also accessible at all higher privilege levels. +Standard CSRs do not have side effects on reads but may have side effects +on writes. + \section{CSR Address Mapping Conventions} The standard RISC-V ISA sets aside a 12-bit encoding space (csr[11:0]) @@ -52,7 +55,7 @@ less-privileged software. \multicolumn{3}{|c|}{CSR Address} & Hex & \multicolumn{1}{c|}{Use and Accessibility}\\ \cline{1-3} [11:10] & [9:8] & [7:4] & & \\ \hline -\multicolumn{5}{|c|}{User CSRs} \\ +\multicolumn{5}{|c|}{Unprivileged and User-Level CSRs} \\ \hline \tt 00 &\tt 00 &\tt XXXX & \tt 0x000-0x0FF & Standard read/write \\ \tt 01 &\tt 00 &\tt XXXX & \tt 0x400-0x4FF & Standard read/write \\ @@ -61,7 +64,7 @@ less-privileged software. \tt 11 &\tt 00 &\tt 10XX & \tt 0xC80-0xCBF & Standard read-only \\ \tt 11 &\tt 00 &\tt 11XX & \tt 0xCC0-0xCFF & Custom read-only \\ \hline -\multicolumn{5}{|c|}{Supervisor CSRs} \\ +\multicolumn{5}{|c|}{Supervisor-Level CSRs} \\ \hline \tt 00 &\tt 01 &\tt XXXX & \tt 0x100-0x1FF & Standard read/write \\ \tt 01 &\tt 01 &\tt 0XXX & \tt 0x500-0x57F & Standard read/write \\ @@ -74,7 +77,7 @@ less-privileged software. \tt 11 &\tt 01 &\tt 10XX & \tt 0xD80-0xDBF & Standard read-only \\ \tt 11 &\tt 01 &\tt 11XX & \tt 0xDC0-0xDFF & Custom read-only \\ \hline -\multicolumn{5}{|c|}{Hypervisor CSRs} \\ +\multicolumn{5}{|c|}{Hypervisor and VS CSRs} \\ \hline \tt 00 &\tt 10 &\tt XXXX & \tt 0x200-0x2FF & Standard read/write \\ \tt 01 &\tt 10 &\tt 0XXX & \tt 0x600-0x67F & Standard read/write \\ @@ -87,7 +90,7 @@ less-privileged software. \tt 11 &\tt 10 &\tt 10XX & \tt 0xE80-0xEBF & Standard read-only \\ \tt 11 &\tt 10 &\tt 11XX & \tt 0xEC0-0xEFF & Custom read-only \\ \hline -\multicolumn{5}{|c|}{Machine CSRs} \\ +\multicolumn{5}{|c|}{Machine-Level CSRs} \\ \hline \tt 00 &\tt 11 &\tt XXXX & \tt 0x300-0x3FF & Standard read/write \\ \tt 01 &\tt 11 &\tt 0XXX & \tt 0x700-0x77F & Standard read/write \\ @@ -139,8 +142,8 @@ accesses. Currently, the counters are the only shadowed CSRs. Tables~\ref{ucsrnames}--\ref{mcsrnames1} list the CSRs that have currently been allocated CSR addresses. The timers, counters, and -floating-point CSRs are standard user-level CSRs, as well as the -additional user trap registers added by the N extension. The other +floating-point CSRs are standard unprivileged CSRs. +The other registers are used by privileged code, as described in the following chapters. Note that not all registers are required on all implementations. @@ -151,28 +154,14 @@ implementations. \hline Number & Privilege & Name & Description \\ \hline -\multicolumn{4}{|c|}{User Trap Setup} \\ -\hline -\tt 0x000 & URW &\tt ustatus & User status register. \\ -\tt 0x004 & URW &\tt uie & User interrupt-enable register. \\ -\tt 0x005 & URW &\tt utvec & User trap handler base address. \\ -\hline -\multicolumn{4}{|c|}{User Trap Handling} \\ -\hline -\tt 0x040 & URW &\tt uscratch & Scratch register for user trap handlers. \\ -\tt 0x041 & URW &\tt uepc & User exception program counter. \\ -\tt 0x042 & URW &\tt ucause & User trap cause. \\ -\tt 0x043 & URW &\tt utval & User bad address or instruction. \\ -\tt 0x044 & URW &\tt uip & User interrupt pending. \\ -\hline -\multicolumn{4}{|c|}{User Floating-Point CSRs} \\ +\multicolumn{4}{|c|}{Unprivileged Floating-Point CSRs} \\ \hline \tt 0x001 & URW &\tt fflags & Floating-Point Accrued Exceptions. \\ \tt 0x002 & URW &\tt frm & Floating-Point Dynamic Rounding Mode. \\ \tt 0x003 & URW &\tt fcsr & Floating-Point Control and Status Register ({\tt frm} + {\tt fflags}). \\ \hline -\multicolumn{4}{|c|}{User Counter/Timers} \\ +\multicolumn{4}{|c|}{Unprivileged Counter/Timers} \\ \hline \tt 0xC00 & URO &\tt cycle & Cycle counter for RDCYCLE instruction. \\ \tt 0xC01 & URO &\tt time & Timer for RDTIME instruction. \\ @@ -191,7 +180,7 @@ Register ({\tt frm} + {\tt fflags}). \\ \hline \end{tabular} \end{center} -\caption{Currently allocated RISC-V user-level CSR addresses.} +\caption{Currently allocated RISC-V unprivileged CSR addresses.} \label{ucsrnames} \end{table} @@ -204,12 +193,14 @@ Number & Privilege & Name & Description \\ \multicolumn{4}{|c|}{Supervisor Trap Setup} \\ \hline \tt 0x100 & SRW &\tt sstatus & Supervisor status register. \\ -\tt 0x102 & SRW &\tt sedeleg & Supervisor exception delegation register. \\ -\tt 0x103 & SRW &\tt sideleg & Supervisor interrupt delegation register. \\ \tt 0x104 & SRW &\tt sie & Supervisor interrupt-enable register. \\ \tt 0x105 & SRW &\tt stvec & Supervisor trap handler base address. \\ \tt 0x106 & SRW &\tt scounteren & Supervisor counter enable. \\ \hline +\multicolumn{4}{|c|}{Supervisor Configuration} \\ +\hline +\tt 0x10A & SRW &\tt senvcfg & Supervisor environment configuration register. \\ +\hline \multicolumn{4}{|c|}{Supervisor Trap Handling} \\ \hline \tt 0x140 & SRW &\tt sscratch & Scratch register for supervisor trap handlers. \\ @@ -256,6 +247,11 @@ Number & Privilege & Name & Description \\ \tt 0x64A & HRW &\tt htinst & Hypervisor trap instruction (transformed). \\ \tt 0xE12 & HRO &\tt hgeip & Hypervisor guest external interrupt pending. \\ \hline +\multicolumn{4}{|c|}{Hypervisor Configuration} \\ +\hline +\tt 0x60A & HRW &\tt henvcfg & Hypervisor environment configuration register. \\ +\tt 0x61A & HRW &\tt henvcfgh & Additional hypervisor env. conf. register, RV32 only. \\ +\hline \multicolumn{4}{|c|}{Hypervisor Protection and Translation} \\ \hline \tt 0x680 & HRW &\tt hgatp & Hypervisor guest address translation and protection. \\ @@ -267,7 +263,7 @@ Number & Privilege & Name & Description \\ \multicolumn{4}{|c|}{Hypervisor Counter/Timer Virtualization Registers} \\ \hline \tt 0x605 & HRW &\tt htimedelta & Delta for VS/VU-mode timer. \\ -\tt 0x615 & HRW &\tt htimedeltah & Upper 32 bits of {\tt htimedelta}, RV32 only. \\ +\tt 0x615 & HRW &\tt htimedeltah & Upper 32 bits of {\tt htimedelta}, HSXLEN=32 only. \\ \hline \multicolumn{4}{|c|}{Virtual Supervisor Registers} \\ \hline @@ -283,7 +279,7 @@ Number & Privilege & Name & Description \\ \hline \end{tabular} \end{center} -\caption{Currently allocated RISC-V hypervisor-level CSR addresses.} +\caption{Currently allocated RISC-V hypervisor and VS CSR addresses.} \label{hcsrnames} \end{table} @@ -300,6 +296,7 @@ Number & Privilege & Name & Description \\ \tt 0xF12 & MRO &\tt marchid & Architecture ID. \\ \tt 0xF13 & MRO &\tt mimpid & Implementation ID. \\ \tt 0xF14 & MRO &\tt mhartid & Hardware thread ID. \\ +\tt 0xF15 & MRO &\tt mconfigptr & Pointer to configuration data structure. \\ \hline \multicolumn{4}{|c|}{Machine Trap Setup} \\ \hline @@ -322,6 +319,13 @@ Number & Privilege & Name & Description \\ \tt 0x34A & MRW &\tt mtinst & Machine trap instruction (transformed). \\ \tt 0x34B & MRW &\tt mtval2 & Machine bad guest physical address. \\ \hline +\multicolumn{4}{|c|}{Machine Configuration} \\ +\hline +\tt 0x30A & MRW &\tt menvcfg & Machine environment configuration register. \\ +\tt 0x31A & MRW &\tt menvcfgh & Additional machine env. conf. register, RV32 only. \\ +\tt 0x747 & MRW &\tt mseccfg & Machine security configuration register. \\ +\tt 0x757 & MRW &\tt mseccfgh & Additional machine security conf. register, RV32 only. \\ +\hline \multicolumn{4}{|c|}{Machine Memory Protection} \\ \hline %\tt 0x380 & MRW &\tt mbase & Base register. \\ |