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Diffstat (limited to 'src/memory.tex')
| -rw-r--r-- | src/memory.tex | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/memory.tex b/src/memory.tex index f35d247..2cab253 100644 --- a/src/memory.tex +++ b/src/memory.tex @@ -668,7 +668,7 @@ Moreover, since SC is defined to carry dependencies from its source registers to { \tt\small \begin{tabular}{cl||cl} - \multicolumn{4}{c}{Initial values: 0(s0)=1; 0(s1)=1} \\ + \multicolumn{4}{c}{Initial values: 0(s0)=1; 0(s2)=1} \\ \\ \multicolumn{2}{c}{Hart 0} & \multicolumn{2}{c}{Hart 1} \\ \hline @@ -1230,6 +1230,15 @@ For example, the LR must also be made to respect any data dependencies that the Likewise, the effect a FENCE~R,R elsewhere in the same hart must also be made to apply to the SC, which would not otherwise respect that fence. The emulator may achieve this effect by simply mapping AMOs onto {\tt lr.aq;~<op>;~sc.aqrl}, matching the mapping used elsewhere for fully ordered atomics. +These C11/C++11 mappings require the platform to provide the following Physical Memory Attributes (as defined in the RISC-V Privileged ISA) for all memory: +\begin{itemize} + \item main memory + \item coherent + \item AMOArithmetic + \item RsrvEventual +\end{itemize} +Platforms with different attributes may require different mappings, or require platform-specific SW (e.g., memory-mapped I/O). + \section{Implementation Guidelines} The RVWMO and RVTSO memory models by no means preclude microarchitectures from employing sophisticated speculation techniques or other forms of optimization in order to deliver higher performance. @@ -1328,7 +1337,6 @@ We expect that any or all of the following possible future extensions would be c \begin{itemize} \item `V' vector ISA extensions - \item A transactional memory subset of the `T' ISA extension \item `J' JIT extension \item Native encodings for load and store opcodes with {\em aq} and {\em rl} set \item Fences limited to certain addresses |