diff options
Diffstat (limited to 'src/machine.adoc')
| -rw-r--r-- | src/machine.adoc | 155 |
1 files changed, 148 insertions, 7 deletions
diff --git a/src/machine.adoc b/src/machine.adoc index 76f42c3..f275d99 100644 --- a/src/machine.adoc +++ b/src/machine.adoc @@ -368,20 +368,87 @@ S-level ISA. [[mstatusreg-rv32]] .Machine-mode status (`mstatus`) register for RV32 -include::images/bytefield/mstatusreg-rv32.adoc[] +[wavedrom, ,svg] +.... +{reg: [ + {bits: 1, name: 'WPRI'}, + {bits: 1, name: 'SIE'}, + {bits: 1, name: 'WPRI'}, + {bits: 1, name: 'MIE'}, + {bits: 1, name: 'WPRI'}, + {bits: 1, name: 'SPIE'}, + {bits: 1, name: 'UBE'}, + {bits: 1, name: 'MPIE'}, + {bits: 1, name: 'SPP'}, + {bits: 2, name: 'VS[1:0]'}, + {bits: 2, name: 'MPP[1:0]'}, + {bits: 2, name: 'FS[1:0]'}, + {bits: 2, name: 'XS[1:0]'}, + {bits: 1, name: 'MPRV'}, + {bits: 1, name: 'SUM'}, + {bits: 1, name: 'MXR'}, + {bits: 1, name: 'TVM'}, + {bits: 1, name: 'TW'}, + {bits: 1, name: 'TSR'}, + {bits: 1, name: 'SPELP'}, + {bits: 7, name: 'WPRI'}, + {bits: 1, name: 'SD'}, +], config:{lanes: 2, hspace:1024}} +.... -include::images/bytefield/mstatusreg.adoc[] [[mstatusreg]] .Machine-mode status (`mstatus`) register for RV64 -include::images/bytefield/mstatusreg2.adoc[] - +[wavedrom, ,svg] +.... +{reg: [ + {bits: 1, name: 'WPRI'}, + {bits: 1, name: 'SIE'}, + {bits: 1, name: 'WPRI'}, + {bits: 1, name: 'MIE'}, + {bits: 1, name: 'WPRI'}, + {bits: 1, name: 'SPIE'}, + {bits: 1, name: 'UBE'}, + {bits: 1, name: 'MPIE'}, + {bits: 1, name: 'SPP'}, + {bits: 2, name: 'VS[1:0]'}, + {bits: 2, name: 'MPP[1:0]'}, + {bits: 2, name: 'FS[1:0]'}, + {bits: 2, name: 'XS[1:0]'}, + {bits: 1, name: 'MPRV'}, + {bits: 1, name: 'SUM'}, + {bits: 1, name: 'MXR'}, + {bits: 1, name: 'TVM'}, + {bits: 1, name: 'TW'}, + {bits: 1, name: 'TSR'}, + {bits: 1, name: 'SPELP'}, + {bits: 8, name: 'WPRI'}, + {bits: 2, name: 'UXL[1:0]'}, + {bits: 2, name: 'SXL[1:0]'}, + {bits: 1, name: 'SBE'}, + {bits: 1, name: 'MBE'}, + {bits: 1, name: 'GVA'}, + {bits: 1, name: 'MPV'}, + {bits: 1, name: 'WPRI'}, + {bits: 1, name: 'MPELP'}, + {bits: 21, name: 'WPRI'}, + {bits: 1, name: 'SD'}, +], config:{lanes: 4, hspace:1024}} +.... For RV32 only, `mstatush` is a 32-bit read/write register formatted as shown in <<mstatushreg>>. Bits 30:4 of `mstatush` generally contain the same fields found in bits 62:36 of `mstatus` for RV64. Fields SD, SXL, and UXL do not exist in `mstatush`. [[mstatushreg]] .Additional machine-mode status (`mstatush`) register for RV32. -include::images/bytefield/mstatushreg.adoc[] +[wavedrom, ,svg] +.... +{reg: [ + {bits: 4, name: 'WPRI'}, + {bits: 1, name: 'SBE'}, + {bits: 1, name: 'MBE'}, + {bits: 26, name: 'WPRI'}, +], config:{lanes: 1, hspace:1024}} +.... [[privstack]] ===== Privilege and Global Interrupt-Enable Stack in `mstatus` register @@ -1067,6 +1134,15 @@ their context to be saved and restored to service asynchronous interrupts, unless the interrupt results in a user-level context swap. ==== +===== Previous Expected Landing Pad (ELP) State in `mstatus` Register + +The Zicfilp extension adds the `SPELP` and `MPELP` fields that hold the previous +`ELP`, and are updated as specified in <<ZICFILP_FORWARD_TRAPS>>. The +*__x__*`PELP` fields are encoded as follows: + +* 0 - `NO_LP_EXPECTED` - no landing pad instruction expected. +* 1 - `LP_EXPECTED` - a landing pad instruction is expected. + ==== Machine Trap-Vector Base-Address (`mtvec`) Register The `mtvec` register is an MXLEN-bit *WARL* read/write register that holds @@ -1942,6 +2018,13 @@ two cases (or alternatively, the system configuration information can be interrogated to install the appropriate trap handling before runtime). ==== +On a trap caused by a software check exception, the `mtval` register holds +the cause for the exception. The following encodings are defined: + +* 0 - No information provided. +* 2 - Landing Pad Fault. Defined by the Zicfilp extension (<<priv-forward>>). +* 3 - Shadow Stack Fault. Defined by the Zicfiss extension (<<priv-backward>>). + For other traps, `mtval` is set to zero, but a future standard may redefine `mtval`’s setting for other traps. @@ -2000,7 +2083,25 @@ privileged than M. [#menvcfgreg] .Machine environment configuration (`menvcfg`) register. -include::images/bytefield/menvcfgreg.adoc[] +[wavedrom, ,svg] +.... +{reg: [ + {bits: 1, name: 'FIOM'}, + {bits: 1, name: 'WPRI'}, + {bits: 1, name: 'LPE'}, + {bits: 1, name: 'SSE'}, + {bits: 2, name: 'CBIE'}, + {bits: 1, name: 'CBCFE'}, + {bits: 1, name: 'CBZE'}, + {bits: 24, name: 'WPRI'}, + {bits: 2, name: 'PMM'}, + {bits: 26, name: 'WPRI'}, + {bits: 1, name: 'CDE'}, + {bits: 1, name: 'ADUE'}, + {bits: 1, name: 'PBMTE'}, + {bits: 1, name: 'STCE'}, +], config:{lanes: 4, hspace:1024}} +.... If bit FIOM (Fence of I/O implies Memory) is set to one in `menvcfg`, FENCE instructions executed in modes less privileged than M are modified @@ -2091,6 +2192,26 @@ The definition of the PMM field will be furnished by the forthcoming Smnpm extension. Its allocation within `menvcfg` may change prior to the ratification of that extension. +The Zicfilp extension adds the `LPE` field in `menvcfg`. When the `LPE` field is +set to 1 and S-mode is implemented, the Zicfilp extension is enabled in S-mode. +If `LPE` field is set to 1 and S-mode is not implemented, the Zicfilp extension +is enabled in U-mode. When the `LPE` field is 0, the Zicfilp extension is not +enabled in S-mode, and the following rules apply to S-mode. If the `LPE` field +is 0 and S-mode is not implemented, then the same rules apply to U-mode. + +* The hart does not update the `ELP` state; it remains as `NO_LP_EXPECTED`. +* The `LPAD` instruction operates as a no-op. + +The Zicfiss extension adds the `SSE` field to `menvcfg`. When the `SSE` field is +set to 1 the Zicfiss extension is activated in S-mode. When `SSE` field is 0, +the following rules apply to privilege modes that are less than M: + +* 32-bit Zicfiss instructions will revert to their behavior as defined by Zimop. +* 16-bit Zicfiss instructions will revert to their behavior as defined by Zcmop. +* The `pte.xwr=010b` encoding in VS/S-stage page tables becomes reserved. +* The `henvcfg.SSE` and `senvcfg.SSE` fields will read as zero and are read-only. +* `SSAMOSWAP.W/D` raises an illegal-instruction exception. + When XLEN=32, `menvcfgh` is a 32-bit read/write register that aliases bits 63:32 of `menvcfg`. The `menvcfgh` register does not exist when XLEN=64. @@ -2105,7 +2226,19 @@ shown in <<mseccfg>>, that controls security features. [[mseccfg]] .Machine security configuration (`mseccfg`) register. -include::images/bytefield/mseccfg.adoc[] +[wavedrom, ,svg] +.... +{reg: [ + {bits: 1, name: 'MML'}, + {bits: 1, name: 'MMWP'}, + {bits: 1, name: 'RLB'}, + {bits: 5, name: 'WPRI'}, + {bits: 1, name: 'USEED'}, + {bits: 1, name: 'SSEED'}, + {bits: 1, name: 'MLPE'}, + {bits: 53, name: 'WPRI'}, +], config:{lanes: 4, hspace:1024}} +.... The definitions of the SSEED and USEED fields will be furnished by the forthcoming entropy-source extension, Zkr. Their allocations within @@ -2119,6 +2252,14 @@ The definition of the PMM field will be furnished by the forthcoming Smmpm extension. Its allocation within `mseccfg` may change prior to the ratification of that extension. +The Zicfilp extension adds the `MLPE` field in `mseccfg`. When `MLPE` field is +1, Zicfilp extension is enabled in M-mode. When the `MLPE` field is 0, the +Zicfilp extension is not enabled in M-mode and the following rules apply to +M-mode. + +* The hart does not update the `ELP` state; it remains as `NO_LP_EXPECTED`. +* The `LPAD` instruction operates as a no-op. + When XLEN=32 only, `mseccfgh` is a 32-bit read/write register that aliases bits 63:32 of `mseccfg`. Register `mseccfgh` does not exist when XLEN=64. |