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Diffstat (limited to 'src/intro.adoc')
| -rw-r--r-- | src/intro.adoc | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/intro.adoc b/src/intro.adoc index 6fc871b..9b86442 100644 --- a/src/intro.adoc +++ b/src/intro.adoc @@ -33,7 +33,7 @@ efficiency. * An ISA that simplifies experiments with new privileged architecture designs. -[TIP] +[NOTE] ==== Commentary on our design decisions is formatted as in this paragraph. This non-normative text can be skipped if the reader is only interested @@ -64,7 +64,7 @@ volume provides the design of the first ("classic") privileged architecture. The manuals use IEC 80000-13:2008 conventions, with a byte of 8 bits. -[TIP] +[NOTE] ==== In the unprivileged ISA design, we tried to remove any dependence on particular microarchitectural features, such as cache line size, or on @@ -144,7 +144,7 @@ environments for guest operating systems. harts on an underlying x86 system, and which can provide either a user-level or a supervisor-level execution environment. -[TIP] +[NOTE] ==== A bare hardware platform can be considered to define an EEI, where the accessible harts, memory, and other devices populate the environment, @@ -176,7 +176,7 @@ constitute forward progress: * Any other event defined by an extension to constitute forward progress. -[TIP] +[NOTE] ==== The term hart was introduced in the work on Lithe cite:[lithe-pan-hotpar09] and cite:[lithe-pan-pldi10] to provide a term to represent an abstract execution resource as opposed to a software thread @@ -221,16 +221,16 @@ integer variants, RV32I and RV64I, described in <<rv32>> and <<rv64>>, which provide 32-bit or 64-bit address spaces respectively. We use the term XLEN to refer to the width of an integer register in bits (either 32 or 64). -<<rv32e, Chapter 6>> describes the RV32E and RV64E subset variants of the +<<rv32e>> describes the RV32E and RV64E subset variants of the RV32I or RV64I base instruction sets respectively, which have been added to support small microcontrollers, and which have half the number of integer registers. -<<rv128, Chapter 8>> sketches a future RV128I variant of the +<<rv128>> sketches a future RV128I variant of the base integer instruction set supporting a flat 128-bit address space (XLEN=128). The base integer instruction sets use a two's-complement representation for signed integer values. -[TIP] +[NOTE] ==== Although 64-bit address spaces are a requirement for larger systems, we believe 32-bit address spaces will remain adequate for many embedded and @@ -382,7 +382,7 @@ harts may be entirely the same, or entirely different, or may be partly different but sharing some subset of resources, mapped into the same or different address ranges. -[TIP] +[NOTE] ==== For a purely "bare metal" environment, all harts may see an identical address space, accessed entirely by physical addresses. However, when @@ -552,7 +552,7 @@ instructions. These instructions are considered to be of minimal length: bits. The encoding with bits [ILEN-1:0] all ones is also illegal; this instruction is considered to be ILEN bits long. -[TIP] +[NOTE] ==== We consider it a feature that any length of instruction containing all zero bits is not legal, as this quickly traps erroneous jumps into @@ -587,7 +587,7 @@ instruction specification. (((bi-endian))) (((endian, bi-))) -[TIP] +[NOTE] ==== We originally chose little-endian byte ordering for the RISC-V memory system because little-endian systems are currently dominant commercially |