diff options
Diffstat (limited to 'src/c.tex')
| -rw-r--r-- | src/c.tex | 11 |
1 files changed, 7 insertions, 4 deletions
@@ -1144,7 +1144,7 @@ valid C instructions will eventually complete. A portion of the RVC encoding space is reserved for microarchitectural HINTs. Like the HINTs in the RV32I base ISA (see Section~\ref{sec:rv32i-hints}), these instructions do not modify any architectural state, except for advancing -the {\tt pc} and the instructions-retired counter {\tt instret}. HINTs are +the {\tt pc} and any applicable performance counters. HINTs are executed as no-ops on implementations that ignore them. RVC HINTs are encoded as computational instructions that do not modify the @@ -1163,9 +1163,12 @@ example, \mbox{C.ADD {\em x0}, {\em t0}} might not encode the same HINT as \mbox{ADD {\em x0}, {\em x0}, {\em t0}}. \begin{commentary} -We expect the static and dynamic frequency of HINT code points will vary -dramatically. Decoupling the RVC and RVI HINT mappings allows the scarce RVC -HINT space to be allocated to the most popular HINTs. +The primary reason to not require an RVC HINT to expand to an RVI HINT +is that HINTs are unlikely to be compressible in the same manner as +the underlying computational instruction. Also, decoupling the RVC +and RVI HINT mappings allows the scarce RVC HINT space to be allocated +to the most popular HINTs, and in particular, to HINTs that are +amenable to macro-op fusion. \end{commentary} Table~\ref{tab:rvc-hints} lists all RVC HINT code points. For RV32C, 78\% of |