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diff --git a/src/c-st-ext.adoc b/src/c-st-ext.adoc index 79904d8..f750a33 100644 --- a/src/c-st-ext.adoc +++ b/src/c-st-ext.adoc @@ -1,11 +1,11 @@ [[compressed]] -== `C` Standard Extension for Compressed Instructions, Version 2.0 +== C Standard Extension for Compressed Instructions, Version 2.0 This chapter describes the current proposal for the RISC-V standard -compressed instruction-set extension, named `C`, which reduces static +compressed instruction-set extension, named _C_, which reduces static and dynamic code size by adding short 16-bit instruction encodings for common operations. The C extension can be added to any of the base ISAs -(RV32, RV64, RV128), and we use the generic term `RVC` to cover any of +(RV32, RV64, RV128), and we use the generic term _RVC_ to cover any of these. Typically, 50%–60% of the RISC-V instructions in a program can be replaced with RVC instructions, resulting in a 25%–30% code-size reduction. @@ -17,8 +17,8 @@ of common 32-bit RISC-V instructions when: * the immediate or address offset is small, or -* one of the registers is the zero register (`x0`), the ABI link register -(`x1`), or the ABI stack pointer (`x2`), or +* one of the registers is the zero register (_x0_), the ABI link register +(_x1_), or the ABI stack pointer (_x2_), or * the destination register and the first source register are identical, or @@ -177,7 +177,7 @@ Table <<rvcopcodemap>> shows the nine compressed instruction formats. CR, CI, and CSS can use any of the 32 RVI registers, but CIW, CL, CS, CA, and CB are limited to just 8 of them. Table <<registers>> lists these popular registers, which -correspond to registers `x8` to `x15`. Note that there is a separate +correspond to registers _x8_ to _x15_. Note that there is a separate version of load and store instructions that use the stack pointer as the base address register, since saving to and restoring from the stack are so prevalent, and that they use the CI and CSS formats to allow access @@ -187,7 +187,7 @@ ADDI4SPN instruction. [NOTE] ==== The RISC-V ABI was changed to make the frequently used registers map to -registers `x8`–`x15`. This simplifies the decompression decoder by +registers *x8*–*x15*. This simplifies the decompression decoder by having a contiguous naturally aligned set of register numbers, and is also compatible with the RV32E base ISA, which only has 16 integer registers. @@ -195,14 +195,14 @@ registers. (((compressed, loads and stores))) Compressed register-based floating-point loads and stores also use the -CL and CS formats respectively, with the eight registers mapping to `f8` -to `f15`. +CL and CS formats respectively, with the eight registers mapping to _f8_ +to _f15_. (((calling convention, standard))) [NOTE] ==== The standard RISC-V calling convention maps the most frequently used -floating-point registers to registers `f8` to `f15`, which allows the +floating-point registers to registers *f8* to *f15*, which allows the same register decompression decoding as for integer register numbers. ==== (((register source specifiers, c-ext))) @@ -223,7 +223,7 @@ position in every instruction, thereby simplifying implementations. ==== For many RVC instructions, zero-valued immediates are disallowed and -`x0` is not a valid 5-bit register specifier. These restrictions free up +_x0_ is not a valid 5-bit register specifier. These restrictions free up encoding space for other instructions requiring fewer operand bits. //include::images/wavedrom/cr-register.adoc[] @@ -267,13 +267,13 @@ CS, CA, and CB formats. |=== |RVC Register Number |000 |001 |010 |011 |100 |101 |110 |111 -|Integer Register Number |`x8` |`x9` |`x10` |`x11` |`x12` |`x13` |`x14`|`x15` +|Integer Register Number |_x8_ |_x9_ |_x10_ |_x11_ |_x12_ |_x13_ |_x14_|_x15_ -|Integer Register ABI Name |`s0` |`s1` |`a0` |`a1` |`a2` |`a3` |`a4`|`a5` +|Integer Register ABI Name |_s0_ |_s1_ |_a0_ |_a1_ |_a2_ |_a3_ |_a4_|_a5_ -|Floating-Point Register Number |`f8` |`f9` |`f10` |`f11` |`f12` |`f13`|`f14` |`f15` +|Floating-Point Register Number |_f8_ |_f9_ |_f10_ |_f11_ |_f12_ |_f13_|_f14_ |_f15_ -|Floating-Point Register ABI Name |`fs0` |`fs1` |`fa0` |`fa1` |`fa2`|`fa3` |`fa4` |`fa5` +|Floating-Point Register ABI Name |_fs0_ |_fs1_ |_fa0_ |_fa1_ |_fa2_|_fa3_ |_fa4_ |_fa5_ |=== @@ -285,7 +285,7 @@ bytes: latexmath:[$\times$]4 for words, latexmath:[$\times$]8 for double words, and latexmath:[$\times$]16 for quad words. RVC provides two variants of loads and stores. One uses the ABI stack -pointer, `x2`, as the base address and can target any data register. The +pointer, _x2_, as the base address and can target any data register. The other can reference one of 8 base address registers and one of 8 data registers. @@ -300,7 +300,7 @@ These instructions use the CI format. C.LWSP loads a 32-bit value from memory into register _rd_. It computes an effective address by adding the _zero_-extended offset, scaled by 4, -to the stack pointer, `x2`. It expands to `lw rd, offset(x2)`. C.LWSP is +to the stack pointer, _x2_. It expands to _lw rd, offset(x2)_. C.LWSP is only valid when latexmath:[$\textit{rd}{\neq}\texttt{x0}$]; the code points with latexmath:[$\textit{rd}{=}\texttt{x0}$] are reserved. (((operations, memory))) @@ -308,28 +308,28 @@ points with latexmath:[$\textit{rd}{=}\texttt{x0}$] are reserved. C.LDSP is an RV64C/RV128C-only instruction that loads a 64-bit value from memory into register _rd_. It computes its effective address by adding the zero-extended offset, scaled by 8, to the stack pointer, -`x2`. It expands to `ld rd, offset(x2)`. C.LDSP is only valid when +_x2_. It expands to _ld rd, offset(x2)_. C.LDSP is only valid when latexmath:[$\textit{rd}{\neq}\texttt{x0}$]; the code points with latexmath:[$\textit{rd}{=}\texttt{x0}$] are reserved. C.LQSP is an RV128C-only instruction that loads a 128-bit value from memory into register _rd_. It computes its effective address by adding -the zero-extended offset, scaled by 16, to the stack pointer, `x2`. It -expands to `lq rd, offset(x2)`. C.LQSP is only valid when +the zero-extended offset, scaled by 16, to the stack pointer, _x2_. It +expands to _lq rd, offset(x2)_. C.LQSP is only valid when latexmath:[$\textit{rd}{\neq}\texttt{x0}$]; the code points with latexmath:[$\textit{rd}{=}\texttt{x0}$] are reserved. C.FLWSP is an RV32FC-only instruction that loads a single-precision floating-point value from memory into floating-point register _rd_. It computes its effective address by adding the _zero_-extended offset, -scaled by 4, to the stack pointer, `x2`. It expands to -`flw rd, offset(x2)`. +scaled by 4, to the stack pointer, _x2_. It expands to +_flw rd, offset(x2)_. C.FLDSP is an RV32DC/RV64DC-only instruction that loads a double-precision floating-point value from memory into floating-point register _rd_. It computes its effective address by adding the -_zero_-extended offset, scaled by 8, to the stack pointer, `x2`. It -expands to `fld rd, offset(x2)`. +_zero_-extended offset, scaled by 8, to the stack pointer, _x2_. It +expands to _fld rd, offset(x2)_. include::images/wavedrom/sp-base-ls-2.adoc[] [sp-base-ls-2] @@ -340,29 +340,29 @@ These instructions use the CSS format. C.SWSP stores a 32-bit value in register _rs2_ to memory. It computes an effective address by adding the _zero_-extended offset, scaled by 4, to -the stack pointer, `x2`. It expands to `sw rs2, offset(x2)`. +the stack pointer, _x2_. It expands to _sw rs2, offset(x2)_. C.SDSP is an RV64C/RV128C-only instruction that stores a 64-bit value in register _rs2_ to memory. It computes an effective address by adding the -_zero_-extended offset, scaled by 8, to the stack pointer, `x2`. It -expands to `sd rs2, offset(x2)`. +_zero_-extended offset, scaled by 8, to the stack pointer, _x2_. It +expands to _sd rs2, offset(x2)_. C.SQSP is an RV128C-only instruction that stores a 128-bit value in register _rs2_ to memory. It computes an effective address by adding the -_zero_-extended offset, scaled by 16, to the stack pointer, `x2`. It -expands to `sq rs2, offset(x2)`. +_zero_-extended offset, scaled by 16, to the stack pointer, _x2_. It +expands to _sq rs2, offset(x2)_. C.FSWSP is an RV32FC-only instruction that stores a single-precision floating-point value in floating-point register _rs2_ to memory. It computes an effective address by adding the _zero_-extended offset, -scaled by 4, to the stack pointer, `x2`. It expands to -`fsw rs2, offset(x2)`. +scaled by 4, to the stack pointer, _x2_. It expands to +_fsw rs2, offset(x2)_. C.FSDSP is an RV32DC/RV64DC-only instruction that stores a double-precision floating-point value in floating-point register _rs2_ to memory. It computes an effective address by adding the -_zero_-extended offset, scaled by 8, to the stack pointer, `x2`. It -expands to `fsd rs2, offset(x2)`. +_zero_-extended offset, scaled by 8, to the stack pointer, _x2_. It +expands to _fsd rs2, offset(x2)_. [NOTE] ==== @@ -422,31 +422,31 @@ These instructions use the CL format. C.LW loads a 32-bit value from memory into register _rd latexmath:[$'$]_. It computes an effective address by adding the _zero_-extended offset, scaled by 4, to the base address in register -_rs1 latexmath:[$'$]_. It expands to `lw rd, offset(rs1)`. +_rs1 latexmath:[$'$]_. It expands to _lw rd, offset(rs1)_. C.LD is an RV64C/RV128C-only instruction that loads a 64-bit value from memory into register _rd latexmath:[$'$]_. It computes an effective address by adding the _zero_-extended offset, scaled by 8, to the base address in register _rs1 latexmath:[$'$]_. It expands to -`ld rd', offset(rs1')`. +_ld rd', offset(rs1')_. C.LQ is an RV128C-only instruction that loads a 128-bit value from memory into register _rd latexmath:[$'$]_. It computes an effective address by adding the _zero_-extended offset, scaled by 16, to the base address in register _rs1 latexmath:[$'$]_. It expands to -`lq rd, offset(rs1)`. +_lq rd, offset(rs1)_. C.FLW is an RV32FC-only instruction that loads a single-precision floating-point value from memory into floating-point register _rd latexmath:[$'$]_. It computes an effective address by adding the _zero_-extended offset, scaled by 4, to the base address in register -_rs1 latexmath:[$'$]_. It expands to `flw rd, offset(rs1)`. +_rs1 latexmath:[$'$]_. It expands to _flw rd, offset(rs1)_. C.FLD is an RV32DC/RV64DC-only instruction that loads a double-precision floating-point value from memory into floating-point register _rd latexmath:[$'$]_. It computes an effective address by adding the _zero_-extended offset, scaled by 8, to the base address in register -_rs1 latexmath:[$'$]_. It expands to `fld rd, offset(rs1)`. +_rs1 latexmath:[$'$]_. It expands to _fld rd, offset(rs1)_. S@S@S@Y@S@Y + & & & & & + @@ -464,32 +464,32 @@ These instructions use the CS format. C.SW stores a 32-bit value in register _rs2 latexmath:[$'$]_ to memory. It computes an effective address by adding the _zero_-extended offset, scaled by 4, to the base address in register _rs1 latexmath:[$'$]_. It -expands to `sw rs2, offset(rs1)`. +expands to _sw rs2, offset(rs1)_. C.SD is an RV64C/RV128C-only instruction that stores a 64-bit value in register _rs2 latexmath:[$'$]_ to memory. It computes an effective address by adding the _zero_-extended offset, scaled by 8, to the base address in register _rs1 latexmath:[$'$]_. It expands to -`sd rs2, offset(rs1)`. +_sd rs2, offset(rs1)_. C.SQ is an RV128C-only instruction that stores a 128-bit value in register _rs2 latexmath:[$'$]_ to memory. It computes an effective address by adding the _zero_-extended offset, scaled by 16, to the base address in register _rs1 latexmath:[$'$]_. It expands to -`sq rs2, offset(rs1)`. +_sq rs2, offset(rs1)_. C.FSW is an RV32FC-only instruction that stores a single-precision floating-point value in floating-point register _rs2 latexmath:[$'$]_ to memory. It computes an effective address by adding the _zero_-extended offset, scaled by 4, to the base address in register -_rs1 latexmath:[$'$]_. It expands to `fsw rs2, offset(rs1)`. +_rs1 latexmath:[$'$]_. It expands to _fsw rs2, offset(rs1)_. C.FSD is an RV32DC/RV64DC-only instruction that stores a double-precision floating-point value in floating-point register _rs2 latexmath:[$'$]_ to memory. It computes an effective address by adding the _zero_-extended offset, scaled by 8, to the base address in register _rs1 latexmath:[$'$]_. It expands to -`fsd rs2, offset(rs1)`. +_fsd rs2, offset(rs1)_. === Control Transfer Instructions @@ -511,14 +511,14 @@ offset[11latexmath:[$\vert$]4latexmath:[$\vert$]9:8latexmath:[$\vert$]10latexmat These instructions use the CJ format. C.J performs an unconditional control transfer. The offset is -sign-extended and added to the `pc` to form the jump target address. C.J +sign-extended and added to the _pc_ to form the jump target address. C.J can therefore target a latexmath:[$\pm$] range. C.J expands to -`jal x0, offset`. +_jal x0, offset_. C.JAL is an RV32C-only instruction that performs the same operation as C.J, but additionally writes the address of the instruction following -the jump (`pc`+2) to the link register, `x1`. C.JAL expands to -`jal x1, offset`. +the jump (_pc_+2) to the link register, _x1_. C.JAL expands to +_jal x1, offset_. E@T@T@Y + & & & + @@ -530,14 +530,14 @@ C.JALR & srclatexmath:[$\neq$]0 & 0 & C2 + These instructions use the CR format. C.JR (jump register) performs an unconditional control transfer to the -address in register _rs1_. C.JR expands to `jalr x0, 0(rs1)`. C.JR is +address in register _rs1_. C.JR expands to _jalr x0, 0(rs1)_. C.JR is only valid when latexmath:[$\textit{rs1}{\neq}\texttt{x0}$]; the code point with latexmath:[$\textit{rs1}{=}\texttt{x0}$] is reserved. C.JALR (jump and link register) performs the same operation as C.JR, but additionally writes the address of the instruction following the jump -(`pc`+2) to the link register, `x1`. C.JALR expands to -`jalr x1, 0(rs1)`. C.JALR is only valid when +(_pc_+2) to the link register, _x1_. C.JALR expands to +_jalr x1, 0(rs1)_. C.JALR is only valid when latexmath:[$\textit{rs1}{\neq}\texttt{x0}$]; the code point with latexmath:[$\textit{rs1}{=}\texttt{x0}$] corresponds to the C.EBREAK instruction. @@ -562,14 +562,14 @@ offset[7:6latexmath:[$\vert$]2:1latexmath:[$\vert$]5] & C1 + These instructions use the CB format. C.BEQZ performs conditional control transfers. The offset is -sign-extended and added to the `pc` to form the branch target address. +sign-extended and added to the _pc_ to form the branch target address. It can therefore target a latexmath:[$\pm$] range. C.BEQZ takes the branch if the value in register _rs1 latexmath:[$'$]_ is zero. It -expands to `beq rs1, x0, offset`. +expands to _beq rs1, x0, offset_. C.BNEZ is defined analogously, but it takes the branch if _rs1 latexmath:[$'$]_ contains a nonzero value. It expands to -`bne rs1, x0, offset`. +_bne rs1, x0, offset_. === Integer Computational Instructions @@ -591,17 +591,17 @@ latexmath:[$\textrm{dest}{\neq}{\left\{0,2\right\}}$] & nzimm[16:12] & C1 + C.LI loads the sign-extended 6-bit immediate, _imm_, into register _rd_. -C.LI expands into `addi rd, x0, imm`. C.LI is only valid when -_rd_latexmath:[$\neq$]`x0`; the code points with _rd_=`x0` encode HINTs. +C.LI expands into _addi rd, x0, imm_. C.LI is only valid when +_rd_latexmath:[$\neq$]_x0_; the code points with _rd_=_x0_ encode HINTs. C.LUI loads the non-zero 6-bit immediate field into bits 17–12 of the destination register, clears the bottom 12 bits, and sign-extends bit 17 into all higher bits of the destination. C.LUI expands into -`lui rd, nzimm`. C.LUI is only valid when +_lui rd, nzimm_. C.LUI is only valid when latexmath:[$\textit{rd}{\neq}{\left\{\texttt{x0},\texttt{x2}\right\}}$], and when the immediate is not equal to zero. The code points with -_nzimm_=0 are reserved; the remaining code points with _rd_=`x0` are -HINTs; and the remaining code points with _rd_=`x2` correspond to the +_nzimm_=0 are reserved; the remaining code points with _rd_=_x0_ are +HINTs; and the remaining code points with _rd_=_x2_ correspond to the C.ADDI16SP instruction. ==== Integer Register-Immediate Operations @@ -621,29 +621,29 @@ C1 + C.ADDI adds the non-zero sign-extended 6-bit immediate to the value in register _rd_ then writes the result to _rd_. C.ADDI expands into -`addi rd, rd, nzimm`. C.ADDI is only valid when -_rd_latexmath:[$\neq$]`x0` and _nzimm_latexmath:[$\neq$]0. The code -points with _rd_=`x0` encode the C.NOP instruction; the remaining code +_addi rd, rd, nzimm_. C.ADDI is only valid when +_rd_latexmath:[$\neq$]_x0_ and _nzimm_latexmath:[$\neq$]0. The code +points with _rd_=_x0_ encode the C.NOP instruction; the remaining code points with _nzimm_=0 encode HINTs. C.ADDIW is an RV64C/RV128C-only instruction that performs the same computation but produces a 32-bit result, then sign-extends result to 64 -bits. C.ADDIW expands into `addiw rd, rd, imm`. The immediate can be -zero for C.ADDIW, where this corresponds to ` sext.w rd`. C.ADDIW is -only valid when _rd_latexmath:[$\neq$]`x0`; the code points with -_rd_=`x0` are reserved. +bits. C.ADDIW expands into _addiw rd, rd, imm_. The immediate can be +zero for C.ADDIW, where this corresponds to _sext.w rd_. C.ADDIW is +only valid when _rd_latexmath:[$\neq$]_x0_; the code points with +_rd_=_x0_ are reserved. C.ADDI16SP shares the opcode with C.LUI, but has a destination field of -`x2`. C.ADDI16SP adds the non-zero sign-extended 6-bit immediate to the -value in the stack pointer (`sp`=`x2`), where the immediate is scaled to +_x2_. C.ADDI16SP adds the non-zero sign-extended 6-bit immediate to the +value in the stack pointer (_sp_=_x2_), where the immediate is scaled to represent multiples of 16 in the range (-512,496). C.ADDI16SP is used to adjust the stack pointer in procedure prologues and epilogues. It -expands into `addi x2, x2, nzimm`. C.ADDI16SP is only valid when +expands into _addi x2, x2, nzimm_. C.ADDI16SP is only valid when _nzimm_latexmath:[$\neq$]0; the code point with _nzimm_=0 is reserved. [NOTE] ==== -In the standard RISC-V calling convention, the stack pointer `sp` is +In the standard RISC-V calling convention, the stack pointer *sp* is always 16-byte aligned. ==== @@ -656,9 +656,9 @@ nzuimm[5:4latexmath:[$\vert$]9:6latexmath:[$\vert$]2latexmath:[$\vert$]3] & dest & C0 + C.ADDI4SPN is a CIW-format instruction that adds a _zero_-extended -non-zero immediate, scaled by 4, to the stack pointer, `x2`, and writes -the result to `rd`. This instruction is used to generate pointers to -stack-allocated variables, and expands to `addi rd, x2, nzuimm`. +non-zero immediate, scaled by 4, to the stack pointer, _x2_, and writes +the result to _rd_. This instruction is used to generate pointers to +stack-allocated variables, and expands to _addi rd, x2, nzuimm_. C.ADDI4SPN is only valid when _nzuimm_latexmath:[$\neq$]0; the code points with _nzuimm_=0 are reserved. @@ -672,13 +672,13 @@ C.SLLI is a CI-format instruction that performs a logical left shift of the value in register _rd_ then writes the result to _rd_. The shift amount is encoded in the _shamt_ field. For RV128C, a shift amount of zero is used to encode a shift of 64. C.SLLI expands into -`slli rd, rd, shamt`, except for RV128C with `shamt=0`, which expands to -`slli rd, rd, 64`. +_slli rd, rd, shamt_, except for RV128C with _shamt=0_, which expands to +_slli rd, rd, 64_. For RV32C, _shamt[5]_ must be zero; the code points with _shamt[5]_=1 are designated for custom extensions. For RV32C and RV64C, the shift amount must be non-zero; the code points with _shamt_=0 are HINTs. For -all base ISAs, the code points with _rd_=`x0` are HINTs, except those +all base ISAs, the code points with _rd_=_x0_ are HINTs, except those with _shamt[5]_=1 in RV32C. S@W@Y@S@T@Y + @@ -694,15 +694,15 @@ _rd latexmath:[$'$]_. The shift amount is encoded in the _shamt_ field. For RV128C, a shift amount of zero is used to encode a shift of 64. Furthermore, the shift amount is sign-extended for RV128C, and so the legal shift amounts are 1–31, 64, and 96–127. C.SRLI expands into -`srli rd', rd', shamt`, except for RV128C with `shamt=0`, which -expands to `srli rd, rd, 64`. +_srli rd', rd', shamt_, except for RV128C with _shamt=0_, which +expands to _srli rd, rd, 64_. For RV32C, _shamt[5]_ must be zero; the code points with _shamt[5]_=1 are designated for custom extensions. For RV32C and RV64C, the shift amount must be non-zero; the code points with _shamt_=0 are HINTs. C.SRAI is defined analogously to C.SRLI, but instead performs an -arithmetic right shift. C.SRAI expands to `srai rd, rd, shamt`. +arithmetic right shift. C.SRAI expands to _srai rd, rd, shamt_. [NOTE] ==== @@ -727,7 +727,7 @@ C.ANDI & imm[5] & C.ANDI & dest & imm[4:0] & C1 + C.ANDI is a CB-format instruction that computes the bitwise AND of the value in register _rd latexmath:[$'$]_ and the sign-extended 6-bit immediate, then writes the result to _rd latexmath:[$'$]_. C.ANDI -expands to `andi rd, rd, imm`. +expands to _andi rd, rd, imm_. ==== Integer Register-Register Operations @@ -741,7 +741,7 @@ C.ADD & destlatexmath:[$\neq$]0 & srclatexmath:[$\neq$]0 & C2 + These instructions use the CR format. C.MV copies the value in register _rs2_ into register _rd_. C.MV expands -into `add rd, x0, rs2`. C.MV is only valid when +into _add rd, x0, rs2_. C.MV is only valid when latexmath:[$\textit{rs2}{\neq}\texttt{x0}$]; the code points with latexmath:[$\textit{rs2}{=}\texttt{x0}$] correspond to the C.JR instruction. The code points with @@ -758,7 +758,7 @@ hardware cost. ==== C.ADD adds the values in registers _rd_ and _rs2_ and writes the result -to register _rd_. C.ADD expands into `add rd, rd, rs2`. C.ADD is only +to register _rd_. C.ADD expands into _add rd, rd, rs2_. C.ADD is only valid when latexmath:[$\textit{rs2}{\neq}\texttt{x0}$]; the code points with latexmath:[$\textit{rs2}{=}\texttt{x0}$] correspond to the C.JALR and C.EBREAK instructions. The code points with @@ -781,34 +781,34 @@ These instructions use the CA format. C.AND computes the bitwise AND of the values in registers _rd latexmath:[$'$]_ and _rs2 latexmath:[$'$]_, then writes the result to register _rd latexmath:[$'$]_. C.AND expands into -`and rd, rd, rs2`. +_and rd, rd, rs2_. C.OR computes the bitwise OR of the values in registers _rd latexmath:[$'$]_ and _rs2 latexmath:[$'$]_, then writes the result to register _rd latexmath:[$'$]_. C.OR expands into -`or rd′, rd′, rs2′`. +_or rd′, rd′, rs2′_. C.XOR computes the bitwise XOR of the values in registers _rd latexmath:[$'$]_ and _rs2 latexmath:[$'$]_, then writes the result to register _rd latexmath:[$'$]_. C.XOR expands into -`xor rd', rd', rs2'. +_xor rd', rd', rs2'_. C.SUB subtracts the value in register _rs2 latexmath:[$'$]_ from the value in register _rd latexmath:[$'$]_, then writes the result to register _rd latexmath:[$'$]_. C.SUB expands into -`sub rd', rd', rs2'. +_sub rd', rd', rs2'_. C.ADDW is an RV64C/RV128C-only instruction that adds the values in registers _rd latexmath:[$'$]_ and _rs2 latexmath:[$'$]_, then sign-extends the lower 32 bits of the sum before writing the result to register _rd latexmath:[$'$]_. C.ADDW expands into -`addw rd', rd', rs2'`. +_addw rd', rd', rs2'_. C.SUBW is an RV64C/RV128C-only instruction that subtracts the value in register _rs2 latexmath:[$'$]_ from the value in register _rd latexmath:[$'$]_, then sign-extends the lower 32 bits of the difference before writing the result to register _rd latexmath:[$'$]_. -C.SUBW expands into `subw rd', rd', rs2'`. +C.SUBW expands into _subw rd', rd', rs2'_. [NOTE] ==== @@ -849,8 +849,8 @@ SW@T@T@Y + C.NOP & 0 & 0 & 0 & C1 + C.NOP is a CI-format instruction that does not change any user-visible -state, except for advancing the `pc` and incrementing any applicable -performance counters. C.NOP expands to `nop`. C.NOP is only valid when +state, except for advancing the _pc_ and incrementing any applicable +performance counters. C.NOP expands to _nop_. C.NOP is only valid when _imm_=0; the code points with _imm_latexmath:[$\neq$]0 encode HINTs. ==== Breakpoint Instruction @@ -861,7 +861,7 @@ E@U@Y + & 10 & 2 + C.EBREAK & 0 & C2 + -Debuggers can use the C.EBREAK instruction, which expands to `ebreak`, +Debuggers can use the C.EBREAK instruction, which expands to _ebreak_, to cause control to be transferred back to the debugging environment. C.EBREAK shares the opcode with the C.ADD instruction, but with _rd_ and _rs2_ both zero, thus can also use the CR format. @@ -886,12 +886,12 @@ C instructions will eventually complete. A portion of the RVC encoding space is reserved for microarchitectural HINTs. Like the HINTs in the RV32I base ISA (see <<rv32i-hints>>, these instructions do not -modify any architectural state, except for advancing the `pc` and any +modify any architectural state, except for advancing the _pc_ and any applicable performance counters. HINTs are executed as no-ops on implementations that ignore them. RVC HINTs are encoded as computational instructions that do not modify -the architectural state, either because _rd_=`x0` (e.g. +the architectural state, either because _rd_=_x0_ (e.g. C.ADD _x0_, _t0_), or because _rd_ is overwritten with a copy of itself (e.g. C.ADDI _t0_, 0). @@ -930,22 +930,22 @@ no standard HINTs will ever be defined in this subspace. |C.NOP |_nzimm_latexmath:[$\neq$]0 |63 .6+^.>s|_Reserved for future standard use_ -|C.ADDI | _rd_latexmath:[$\neq$]`x0`, _nzimm_=0 |31 +|C.ADDI | _rd_latexmath:[$\neq$]_x0_, _nzimm_=0 |31 -|C.LI | _rd_=`x0` |64 +|C.LI | _rd_=_x0_ |64 -|C.LUI | _rd_=`x0`, _nzimm_latexmath:[$\neq$]0 |63 +|C.LUI | _rd_=_x0_, _nzimm_latexmath:[$\neq$]0 |63 -|C.MV | _rd_=`x0`, _rs2_latexmath:[$\neq$]`x0` |31 +|C.MV | _rd_=_x0_, _rs2_latexmath:[$\neq$]_x0_ |31 -|C.ADD | _rd_=`x0`, _rs2_latexmath:[$\neq$]`x0` |31 +|C.ADD | _rd_=_x0_, _rs2_latexmath:[$\neq$]_x0_ |31 -|C.SLLI |_rd_=`x0`, _nzimm_latexmath:[$\neq$]0 |31 (RV32), 63 (RV64/128) .5+^.>s|_Designated +|C.SLLI |_rd_=_x0_, _nzimm_latexmath:[$\neq$]0 |31 (RV32), 63 (RV64/128) .5+^.>s|_Designated for custom use_ -|C.SLLI64 | _rd_=`x0` |1 +|C.SLLI64 | _rd_=_x0_ |1 -|C.SLLI64 | _rd_latexmath:[$\neq$]`x0`, RV32 and RV64 only |31 +|C.SLLI64 | _rd_latexmath:[$\neq$]_x0_, RV32 and RV64 only |31 |C.SRLI64 | RV32 and RV64 only |8 |