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-rw-r--r--src/c-st-ext.adoc8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/c-st-ext.adoc b/src/c-st-ext.adoc
index 97aca5f..6bac419 100644
--- a/src/c-st-ext.adoc
+++ b/src/c-st-ext.adoc
@@ -49,7 +49,7 @@ and/or D) is also implemented. In addition, RV32C includes a compressed
jump and link instruction to compress short-range subroutine calls,
where the same opcode is used to compress ADDIW for RV64C and RV128C.
-[TIP]
+[NOTE]
====
Double-precision loads and stores are a significant fraction of static
and dynamic instructions, hence the motivation to include them in the
@@ -100,7 +100,7 @@ instructions in one C instruction.
It is important to note that the C extension is not designed to be a
stand-alone ISA, and is meant to be used alongside a base ISA.
-[TIP]
+[NOTE]
====
Variable-length instruction sets have long been used to improve code
density. For example, the IBM Stretch cite:[stretch], developed in the late 1950s, had
@@ -526,7 +526,7 @@ latexmath:[$\textit{rs1}{\neq}\texttt{x0}$]; the code point with
latexmath:[$\textit{rs1}{=}\texttt{x0}$] corresponds to the C.EBREAK
instruction.
-[TIP]
+[NOTE]
====
Strictly speaking, C.JALR does not expand exactly to a base RVI
instruction as the value added to the PC to form the link address is 2
@@ -707,7 +707,7 @@ C.MV copies the value in register _rs2_ into register _rd_. C.MV expands
into `add rd, x0, rs2`. C.MV is only valid when
`rs2≠x0` the code points with `rs2=x0` correspond to the C.JR instruction. The code points with `rs2≠x0` and `rd=x0` are HINTs.
-[TIP]
+[NOTE]
====
_C.MV expands to a different instruction than the canonical MV
pseudoinstruction, which instead uses ADDI. Implementations that handle