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| -rw-r--r-- | src/priv-preface.tex | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/priv-preface.tex b/src/priv-preface.tex index d7e301b..e606aff 100644 --- a/src/priv-preface.tex +++ b/src/priv-preface.tex @@ -55,6 +55,7 @@ Additionally, the following compatible changes have been made since version most of the same fields as the upper 32 bits of RV64's {\tt mstatus}. \item Defined the mandatory CSR {\tt mconfigptr}, which if nonzero contains the address of a configuration data structure. +\item Designated part of SYSTEM major opcode for custom use. \item Permitted the unconditional delegation of less-privileged interrupts. \item Added optional big-endian and bi-endian support. \item Made priority of load/store/AMO address-misaligned exceptions @@ -62,6 +63,7 @@ Additionally, the following compatible changes have been made since version and access-fault exceptions. \item PMP reset values are now platform-defined. \item An additional 48 optional PMP registers have been defined. +\item Designated \item Software breakpoint exceptions are permitted to write either 0 or the PC to {\em x}\/{\tt tval}. \item Clarified that bare S-mode need not support the SFENCE.VMA instruction. |