diff options
| -rw-r--r-- | src/c.tex | 9 | ||||
| -rw-r--r-- | src/riscv-spec.tex | 2 | ||||
| -rw-r--r-- | src/rvc-instr-table.tex | 6 |
3 files changed, 9 insertions, 8 deletions
@@ -759,8 +759,8 @@ C.LUI expands into {\tt lui rd, nzuimm[17:12]}. \subsection*{Integer Register-Immediate Operations} These integer register-immediate operations are encoded in the CI -format and perform operations on any non-{\tt x0} integer register and -a 6-bit immediate. The immediate cannot be zero. +format and perform operations on an integer register and +a 6-bit immediate. \vspace{-0.4in} \begin{center} @@ -779,7 +779,7 @@ a 6-bit immediate. The immediate cannot be zero. \multicolumn{1}{c|}{op} \\ \hline 3 & 1 & 5 & 5 & 2 \\ -C.ADDI & nzimm[5] & dest & nzimm[4:0] & C1 \\ +C.ADDI & nzimm[5] & dest$\neq$0 & nzimm[4:0] & C1 \\ C.ADDIW & imm[5] & dest$\neq$0 & imm[4:0] & C1 \\ C.ADDI16SP & nzimm[9] & 2 & nzimm[4$\vert$6$\vert$8:7$\vert$5] & C1 \\ \end{tabular} @@ -788,12 +788,13 @@ C.ADDI16SP & nzimm[9] & 2 & nzimm[4$\vert$6$\vert$8:7$\vert$5] & C1 \\ C.ADDI adds the non-zero sign-extended 6-bit immediate to the value in register {\em rd} then writes the result to {\em rd}. C.ADDI expands into {\tt addi rd, rd, nzimm[5:0]}. +C.ADDI is only valid when {\em rd}$\neq${\tt x0}. C.ADDIW is an RV64C/RV128C-only instruction that performs the same computation but produces a 32-bit result, then sign-extends result to 64 bits. C.ADDIW expands into {\tt addiw rd, rd, imm[5:0]}. The immediate can be zero for C.ADDIW, where this corresponds to {\tt -sext.w rd}. +sext.w rd}. C.ADDIW is only valid when {\em rd}$\neq${\tt x0}. C.ADDI16SP shares the opcode with C.LUI, but has a destination field of {\tt x2}. C.ADDI16SP adds the non-zero sign-extended 6-bit immediate to diff --git a/src/riscv-spec.tex b/src/riscv-spec.tex index 5e30588..f276238 100644 --- a/src/riscv-spec.tex +++ b/src/riscv-spec.tex @@ -6,7 +6,7 @@ \input{preamble} -\newcommand{\specrev}{2.2} +\newcommand{\specrev}{2.3-draft} \begin{document} diff --git a/src/rvc-instr-table.tex b/src/rvc-instr-table.tex index b74c929..ce7f6c5 100644 --- a/src/rvc-instr-table.tex +++ b/src/rvc-instr-table.tex @@ -167,10 +167,10 @@ & \multicolumn{3}{|c|}{000} & -\multicolumn{1}{c|}{0} & -\multicolumn{5}{c|}{0} & +\multicolumn{1}{c|}{nzimm[5]} & \multicolumn{5}{c|}{0} & -\multicolumn{2}{c|}{01} & C.NOP \\ +\multicolumn{5}{c|}{nzimm[4:0]} & +\multicolumn{2}{c|}{01} & C.NOP {\em \tiny (HINT, nzimm$\neq$0) } \\ \cline{2-17} & |