diff options
| -rw-r--r-- | src/zfh.adoc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/zfh.adoc b/src/zfh.adoc index d3a8340..77b7437 100644 --- a/src/zfh.adoc +++ b/src/zfh.adoc @@ -104,7 +104,7 @@ Instructions are provided to move bit patterns between the floating-point and integer registers. FMV.X.H moves the half-precision value in floating-point register _rs1_ to a representation in IEEE 754-2008 standard encoding in integer register _rd_, filling the upper -XLEN-16 bits with copies of the floating-point number’s sign bit. +XLEN-16 bits with copies of the floating-point number's sign bit. FMV.H.X moves the half-precision value encoded in IEEE 754-2008 standard encoding from the lower 16 bits of integer register _rs1_ to the @@ -161,7 +161,7 @@ Half-precision addition, subtraction, multiplication, division, and square-root operations can be faithfully emulated by converting the half-precision operands to single-precision, performing the operation using single-precision arithmetic, then converting back to -half-precision. Performing half-precision fused multiply-addition using +half-precision. Cite:[roux:hal-01091186] Performing half-precision fused multiply-addition using this method incurs a 1-ulp error on some inputs for the RNE and RMM rounding modes. |