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-rw-r--r-- | src/hypervisor.tex | 66 |
1 files changed, 36 insertions, 30 deletions
diff --git a/src/hypervisor.tex b/src/hypervisor.tex index 193189f..872177a 100644 --- a/src/hypervisor.tex +++ b/src/hypervisor.tex @@ -815,28 +815,37 @@ interrupt signal selected from {\tt hgeip} by {\tt hstatus}.VGEIN. } The {\tt henvcfg} CSR is an HSXLEN-bit read/write register, -formatted as shown in Figure~\ref{fig:henvcfg}, that controls certain +formatted for HSXLEN=64 as shown in Figure~\ref{fig:henvcfg}, +that controls certain characteristics of the execution environment when virtualization mode V=1. -Only one bit of {\tt henvcfg} is used, but standard \mbox{RISC-V} ISA -extensions may define other fields in this register. \begin{figure}[h!] {\footnotesize \begin{center} -\begin{tabular}{@{}Jc} -\instbitrange{HSXLEN-1}{1} & +\begin{tabular}{c@{}Kcc@{}W@{}Wc} +\instbit{63} & +\instbitrange{62}{8} & +\instbit{7} & +\instbit{6} & +\instbitrange{5}{4} & +\instbitrange{3}{1} & \instbit{0} \\ \hline -\multicolumn{1}{|c|}{\wpri} & +\multicolumn{1}{|c|}{VSTCD} & +\multicolumn{1}{c|}{\wpri} & +\multicolumn{1}{c|}{CBZE} & +\multicolumn{1}{c|}{CBCFE} & +\multicolumn{1}{c|}{CBIE} & +\multicolumn{1}{c|}{\wpri} & \multicolumn{1}{c|}{FIOM} \\ \hline -HSXLEN-1 & 1 \\ +1 & 55 & 1 & 1 & 2 & 3 & 1 \\ \end{tabular} \end{center} } \vspace{-0.1in} -\caption{Hypervisor environment configuration register ({\tt henvcfg}).} +\caption{Hypervisor environment configuration register ({\tt henvcfg}) for HSXLEN=64.} \label{fig:henvcfg} \end{figure} @@ -869,31 +878,28 @@ FIOM=1 and virtualization mode V=1.% \label{tab:henvcfg-FIOM} \end{table} -When HSXLEN=32, {\tt henvcfgh} is a 32-bit read/write register that -generally contains the same fields as bits 63:32 of {\tt henvcfg} when +The definition of the VSTCD field will be furnished by the +forthcoming Sstc extension. +Its allocation within {\tt henvcfg} may change prior to the ratification +of that extension. + +The definition of the CBZE field will be furnished by the +forthcoming Zicboz extension. +Its allocation within {\tt henvcfg} may change prior to the ratification +of that extension. + +The definitions of the CBCFE and CBIE fields will be furnished by the +forthcoming Zicbom extension. +Their allocations within {\tt henvcfg} may change prior to the ratification +of that extension. + +When HSXLEN=32, {\tt henvcfg} contains the same fields as bits 31:0 +of {\tt henvcfg} when HSXLEN=64. +Additionally, when HSXLEN=32, {\tt henvcfgh} is a 32-bit read/write register that +contains the same fields as bits 63:32 of {\tt henvcfg} when HSXLEN=64. Register {\tt henvcfgh} does not exist when HSXLEN=64. -\begin{figure}[h!] -{\footnotesize -\begin{center} -\begin{tabular}{@{}J} -\instbitrange{31}{0} \\ -\hline -\multicolumn{1}{|c|}{\wpri} \\ -\hline -32 \\ -\end{tabular} -\end{center} -} -\vspace{-0.1in} -\caption{% -High-half hypervisor environment configuration register -({\tt henvcfgh}), if HSXLEN=32.% -} -\label{fig:henvcfgh} -\end{figure} - \subsection{Hypervisor Counter-Enable Register ({\tt hcounteren})} The counter-enable register {\tt hcounteren} is a 32-bit register that |