diff options
| -rw-r--r-- | src/rv32.tex | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/src/rv32.tex b/src/rv32.tex index afc6730..99d58f7 100644 --- a/src/rv32.tex +++ b/src/rv32.tex @@ -1213,7 +1213,24 @@ hart or external device can observe any operation in the {\em predecessor} set preceding the FENCE. Chapter~\ref{ch:memorymodel} provides a precise description of the RISC-V memory consistency model. - + +The FENCE instruction also orders memory reads and writes made by the +hart as observed by memory reads and writes made by an external +device. However, FENCE does not order observations of events made by +an external device using any other signaling mechanism. + +\begin{commentary} +A device might observe an access to a memory location via some +external communication mechanism, e.g., a memory-mapped control +register that drives an interrupt signal to an interrupt controller. +This communication is outside the scope of the FENCE ordering +mechanism and hence the FENCE instruction can provide no guarantee on +when a change in the interrupt signal is visible to the interrupt +controller. Specific devices might provide additional ordering +guarantees to reduce software overhead but those are outside the scope +of the RISC-V memory model. +\end{commentary} + The EEI will define what I/O operations are possible, and in particular, which memory addresses when accessed by load and store instructions will be treated and ordered as device input and device output operations respectively |